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TS7001 Arkusz danych(PDF) 3 Page - Silicon Laboratories

Numer części TS7001
Szczegółowy opis  A Micropower, 2-channel, 187.5-ksps, Serial-Output 12-bit SAR ADC
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Producent  SILABS [Silicon Laboratories]
Strona internetowa  http://www.silabs.com
Logo SILABS - Silicon Laboratories

TS7001 Arkusz danych(HTML) 3 Page - Silicon Laboratories

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TS7001
TS7001 Rev. 1.0
Page 3
ELECTRICAL CHARACTERISTICS
VDD = +2.7V to +3.6V; VREF = 2.5V External/internal reference unless otherwise noted; fSCLK = 3 MHz;
TA = TMIN to TMAX, unless otherwise noted.
Parameter
Limit1
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal to Noise + Distortion Ratio (SNR)2
71
dB (typ)
fIN = 10 kHz sine wave, fSAMPLE = 187.5ksps
Total Harmonic Distortion (THD)
−80
dB (typ)
fIN = 10 kHz sine wave, fSAMPLE = 187.5ksps
Peak Harmonic or Spurious Noise
−80
db (typ)
fIN = 10 kHz sine wave, fSAMPLE = 187.5ksps
Intermodulation Distortion (IMD)
Second-Order Terms
−80
dB (typ)
f1 = 9.983 kHz, f2 = 10.05 kHz, fSAMPLE = 187.5ksps
Third-Order Terms
−80
dB (typ)
f1 = 9.983 kHz, f2 = 10.05 kHz, fSAMPLE = 187.5ksps
Channel-to-Channel Isolation
−80
dB (typ)
fIN = 25 kHz
Full-Power Bandwidth
10
MHz (typ)
Measured at 3 dB down
DC ACCURACY(Any channel)
Resolution
12
Bits
Integral Nonlinearity
±1
LSB (max)
VDD = 3V
Differential Nonlinearity
±1
LSB (max)
VDD = 3V; Guaranteed no missing codes to 11 bits
Offset Error
±4
LSB (max)
VDD = 3V, dual-channel mode
±6
LSB (typ)
Single-channel mode
Offset Error Match
0.5
LSB (max)
Gain Error
±2
LSB (typ)
Dual-channel mode
±1
LSB (max)
Single-channel mode, external reference
±6
LSB (typ)
Single-channel mode, internal reference
Gain Error Match
2
LSB (max)
ANALOG INPUT
Input Voltage Range
0 to VREF
V
Single-channel operation
0 to VDD
V
Dual-channel operation
Leakage Current
±5
μA (max)
Input Capacitance
10
pF (typ)
REFERENCE INPUT/OUTPUT
REFIN Input Voltage Range
2.5/VDD
V (min/max)
Single-channel/Dual-channel; Functional from 1.2V
Input Impedance
10
k
Ω (typ)
Very high impedance if internal reference is disabled
REFOUT Output Voltage
2.488/2.513
V (min/max)
Initial accuracy = 0.5%
REFOUT Temperature Coefficient
30
ppm/°C (typ)
LOGIC INPUTS
Input High Voltage, VINH
2.1
V (min)
VDD = 2.7V to 3.6V
Input Low Voltage, VINL
0.8
V (max)
VDD = 2.7V to 3.6V
Input Current, IIN
±1
μA (max)
Typically 10nA, VIN = 0V or VDD
Input Capacitance, CIN
3
10
pF (max)
LOGIC OUTPUTS
Output High Voltage, VOH
VDD − 0.5
V (min)
VDD = 2.7V to 3.6V, ISOURCE = 200 μA
Output Low Voltage, VOL
0.4
V (max)
ISINK = 200 μA
Floating-State Leakage Current
±1
μA (max)
Floating-State Output Capacitance4
10
pF (max)
Output Coding
Straight
(Natural)
Binary
CONVERSION RATE
Throughput Time
16
SCLK cycles
Conversion time plus acquisition time is 187.5ksps,
with 3 MHz Clock
Track-and-Hold Acquisition Time
1.5
SCLK cycles
Conversion Time
14.5
SCLK cycles
4.833
μs (3 MHz Clock)


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