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ADS42B49 Arkusz danych(PDF) 5 Page - Texas Instruments |
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ADS42B49 Arkusz danych(HTML) 5 Page - Texas Instruments |
5 / 65 page 48 47 46 45 42 43 42 41 40 39 38 37 36 35 34 33 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 DRVDD DA6P DA6M DA4P DA4M DA2P DA2M DA0P DA0M DRGND DRVDD CTRL3 CTRL2 CTRL1 AVDD_BUF AVDD DRVDD DB4M DB4P DB6M DB6P DB8M DB8P DB10M DB10P DB12M DB12P RESET SCLK SDATA SEN AVDD Thermal Pad (Connected to DRGND) ADS42B49 www.ti.com SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015 7 Pin Configuration and Functions RGC Package(1) 64-Pin VQFN With Exposed Thermal Pad LVDS Mode - Top View (1) The thermal pad is connected to DRGND. Pin Functions - LVDS Mode PIN I/O DESCRIPTION NAME NO. 17, 18, 21, 24, 27, 28, AGND Input Analog ground 31, 32 AVDD 16, 22, 33 Input Analog power supply AVDD_BUF 34 Input Analog buffer supply CLKM 26 Input Differential clock negative input CLKP 25 Input Differential clock positive input CLKOUTM 56 Output Differential output clock, complement CLKOUTP 57 Output Differential output clock, true Digital control input pins. CTRL1 35 Input Together, these pins control the various power-down modes. Digital control input pins. CTRL2 36 Input Together, these pins control the various power-down modes. Digital control input pins. CTRL3 37 Input Together, these pins control the various power-down modes. DA0P, DA0M 41, 40 Output Channel A differential output data pair, D0 and D1 multiplexed DA2P, DA2M 43, 42 Output Channel A differential output data D2 and D3 multiplexed DA4P, DA4M 45, 44 Output Channel A differential output data D4 and D5 multiplexed DA6P, DA6M 47, 46 Output Channel A differential output data D6 and D7 multiplexed DA8P, DA8M 51, 50 Output Channel A differential output data D8 and D9 multiplexed Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: ADS42B49 |
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