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ADS1118-Q1 Arkusz danych(PDF) 7 Page - Texas Instruments |
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ADS1118-Q1 Arkusz danych(HTML) 7 Page - Texas Instruments |
7 / 41 page SCLK CS DIN DOUT t SCLK t CSSC t SPWH t DIHD t SPWL t CSDOZ t DOHD t DOPD t SCCS t SCSC t CSH t CSDOD t DIST Hi-Z Hi-Z ADS1118-Q1 www.ti.com SBAS740A – OCTOBER 2015 – REVISED NOVEMBER 2015 7.6 Timing Requirements: Serial Interface over operating ambient temperature range and VDD = 2 V to 5.5 V (unless otherwise noted) MIN MAX UNIT tCSSC Delay time, CS falling edge to first SCLK rising edge(1) 100 ns tSCCS Delay time, final SCLK falling edge to CS rising edge 100 ns tCSH Pulse duration, CS high 200 ns tSCLK SCLK period 250 ns tSPWH Pulse duration, SCLK high 100 ns 100 ns tSPWL Pulse duration, SCLK low(2) 28 ms tDIST Setup time, DIN valid before SCLK falling edge 50 ns tDIHD Hold time, DIN valid after SCLK falling edge 50 ns tDOHD Hold time, SCLK rising edge to DOUT invalid 0 ns (1) CS can be tied low permanently in case the serial bus is not shared with any other device. (2) Holding SCLK low longer than 28 ms resets the SPI interface. 7.7 Switching Characteristics: Serial Interface over operating ambient temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Propagation delay time, tCSDOD DOUT load = 20 pF || 100 k Ω to GND 100 ns CS falling edge to DOUT driven Propagation delay time, tDOPD DOUT load = 20 pF || 100 k Ω to GND 0 50 ns SCLK rising edge to valid new DOUT Propagation delay time, tCSDOZ DOUT load = 20 pF || 100 k Ω to GND 100 ns CS rising edge to DOUT high impedance Figure 1. Serial Interface Timing Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: ADS1118-Q1 |
Podobny numer części - ADS1118-Q1 |
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Podobny opis - ADS1118-Q1 |
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