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ADS4122IRGZR Arkusz danych(PDF) 7 Page - Texas Instruments

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Numer części ADS4122IRGZR
Szczegółowy opis  Ultra Low-Power ADC
Download  74 Pages
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Producent  TI1 [Texas Instruments]
Strona internetowa  http://www.ti.com
Logo TI1 - Texas Instruments

ADS4122IRGZR Arkusz danych(HTML) 7 Page - Texas Instruments

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ADS4122, ADS4125, ADS4142, ADS4145
www.ti.com
SBAS520B – FEBRUARY 2011 – REVISED JANUARY 2016
Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is less than |0.3 V|.
This prevents the ESD protection diodes at the clock input pins from turning on.
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range, unless otherwise noted.
(1)
MIN
MAX
UNIT
Supply voltage, AVDD
–0.3
2.1
V
Supply voltage, DRVDD
–0.3
2.1
V
Voltage between AGND and DRGND
–0.3
0.3
V
Voltage between AVDD to DRVDD (when AVDD leads DRVDD)
0
2.1
V
Voltage between DRVDD to AVDD (when DRVDD leads AVDD)
0
2.1
V
Voltage applied to input pins
INP, INM
–0.3
minimum (1.9, AVDD + 0.3)
V
CLKP, CLKM(2), DFS, OE
–0.3
AVDD + 0.3
V
RESET, SCLK, SDATA, SEN
–0.3
3.9
V
Operating free-air temperature, TA
–40
85
°C
Operating junction temperature, TJ
125
°C
Storage temperature, Tstg
–65
150
°C
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±500
(1)
With 0dB gain. See the Gain section in the Application Information for relation between input voltage range and gain.
(2)
See Application Information.
7.3 Recommended Operating Conditions
Over operating free-air temperature range, unless otherwise noted.
MIN
NOM
MAX
UNIT
SUPPLIES
AVDD
Analog supply voltage
1.7
1.8
1.9
V
DRVDD
Digital supply voltage
1.7
1.8
1.9
V
ANALOG INPUTS
Differential input voltage range(1)
2
VPP
Input common-mode voltage
VCM ± 0.05
V
Maximum analog input frequency with 2-VPP input amplitude
(2)
400
MHz
Maximum analog input frequency with 1-VPP input amplitude
(2)
800
MHz
CLOCK INPUT
Input clock sample rate
ADS4122/ADS4142, low-speed mode enabled by
default
20
65
MSPS
ADS4125/ADS4145, low-speed mode enabled
20
80
ADS4125/ADS4145, low-speed mode disabled
>80
125
Input clock amplitude
differential (VCLKP
VCLKM)
Sine wave, ac-coupled
0.2
1.5
VPP
LVPECL, ac-coupled
1.6
LVDS, ac-coupled
0.7
LVCMOS, single-ended, ac-coupled
1.8
V


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