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ADS4145IRGZR Arkusz danych(PDF) 6 Page - Texas Instruments |
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ADS4145IRGZR Arkusz danych(HTML) 6 Page - Texas Instruments |
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6 / 74 page  6 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520B – FEBRUARY 2011 – REVISED JANUARY 2016 www.ti.com Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Pin Functions - CMOS Mode (continued) PIN I/O DESCRIPTION NAME ADS412x ADS414x D3 40 38 O 12-bit/14-bit CMOS output data D4 41 39 O 12-bit/14-bit CMOS output data D5 42 40 O 12-bit/14-bit CMOS output data D6 43 41 O 12-bit/14-bit CMOS output data D7 44 42 O 12-bit/14-bit CMOS output data D8 45 43 O 12-bit/14-bit CMOS output data D9 46 44 O 12-bit/14-bit CMOS output data D10 47 45 O 12-bit/14-bit CMOS output data D11 48 46 O 12-bit/14-bit CMOS output data D12 — 47 O 12-bit/14-bit CMOS output data D13 — 48 O 12-bit/14-bit CMOS output data DFS 6 6 I Data format select input. This pin sets the DATA FORMAT (twos complement or offset binary) and the LVDS/CMOS output interface type. See Table 4 for detailed information. DRGND 1, 36, PAD 1, 36, PAD I Digital and output buffer ground DRVDD 2, 35 2, 35 I 1.8-V digital and output buffer supply INM 16 16 I Differential analog input, negative INP 15 15 I Differential analog input, positive NC 21, 31, 32, 33, 34 21, 31, 32 – Do not connect OE 7 7 I Output buffer enable input, active high; this pin has an internal 180-k Ω pull-up resistor to DRVDD. OVR_SDOUT 3 3 O This pin functions as an out-of-range indicator after reset, when register bit READOUT = 0, and functions as a serial register readout pin when READOUT = 1. RESERVED 23 23 I Digital control pin, reserved for future use RESET 30 30 I Serial interface RESET input. When using the serial interface mode, the internal registers must initialize through hardware RESET by applying a high pulse on this pin or by using the software reset option; refer to the Serial Interface section. When RESET is tied high, the internal registers are reset to the default values. In this condition, SEN can be used as an analog control pin. RESET has an internal 180-k Ω pull-down resistor. SCLK 29 29 I This pin functions as a serial interface clock input when RESET is low. When RESET is high, SCLK has no function and should be tied to ground. This pin has an internal 180-k Ω pull-down resistor. SDATA 28 28 I This pin functions as a serial interface data input when RESET is low. When RESET is high, SDATA functions as a STANDBY control pin (see Table 6). This pin has an internal 180-k Ω pull- down resistor. SEN 27 27 I This pin functions as a serial interface enable input when RESET is low. When RESET is high, SEN has no function and should be tied to AVDD. This pin has an internal 180-k Ω pull-up resistor to AVDD. UNUSED 4 4 – Unused pin in CMOS mode VCM 13 13 O Outputs the common-mode voltage (0.95 V) that can be used externally to bias the analog input pins. |
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