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ADS8557IPMR Arkusz danych(PDF) 7 Page - Texas Instruments |
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ADS8557IPMR Arkusz danych(HTML) 7 Page - Texas Instruments |
7 / 47 page 7 ADS8556, ADS8557, ADS8558 www.ti.com SBAS404D – OCTOBER 2006 – REVISED FEBRUARY 2016 Product Folder Links: ADS8556 ADS8557 ADS8558 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. PARALLEL INTERFACE (PAR/SER = 0) SERIAL INTERFACE (PAR/SER = 1) REFEN/WR 63 DI Hardware mode (HW/SW = 0): Internal reference enable input. When high, the internal reference is enabled (the reference buffers are to be enabled). When low, the internal reference is disabled and an external reference is applied at REFIO. Hardware mode (HW/SW = 0): Internal reference enable input. When high, the internal reference is enabled (the reference buffers are to be enabled). When low, the internal reference is disabled and an external reference must be applied at REFIO. Software mode (HW/SW = 1): Write input. The parallel data input is enabled, when CS and WR are low. The internal reference is enabled by the CR bit C25 (REFEN). Software mode (HW/SW = 1): Connect to BGND or BVDD. The internal reference is enabled by CR bit C25 (REFEN). DB15 64 DIO Data bit 15 (MSB) input/output. Output is '0' for the ADS8557/8. Connect to BGND. (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Supply voltage, HVDD to AGND –0.3 18 V Supply voltage, HVSS to AGND –18 0.3 V Supply voltage, AVDD to AGND –0.3 6 V Supply voltage, BVDD to BGND –0.3 6 V Analog input voltage HVSS – 0.3 HVDD + 0.3 V Reference input voltage with respect to AGND AGND – 0.3 AVDD + 0.3 V Digital input voltage with respect to BGND BGND – 0.3 BVDD + 0.3 V Ground voltage difference AGND to BGND ±0.3 V Input current to all pins except supply –10 10 mA Maximum virtual junction temperature, TJ 150 °C Storage Temperature, Tstg -65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 JEDEC standard 22, test method A114-C.01(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101 JEDEC standard 22, test method C101(2) ±500 |
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