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ADC12D1600CIUT Arkusz danych(PDF) 4 Page - Texas Instruments |
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ADC12D1600CIUT Arkusz danych(HTML) 4 Page - Texas Instruments |
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4 / 86 page  VA AGND VA AGND 100 VBIAS 50k 50k VA AGND VA AGND 100 VA AGND VA AGND 100 VBIAS 50k 50k ADC12D1000, ADC12D1600 SNAS480N – MAY 2010 – REVISED AUGUST 2015 www.ti.com Pin Functions: Analog Front-End and Clock Balls PIN I/O EQUIVALENT CIRCUIT DESCRIPTION NAME NO. Differential Converter Sampling Clock. In the Non- DES Mode, the analog inputs are sampled on the positive transitions of this clock signal. In the DES CLK+/- U2/V1 I Mode, the selected input is sampled on both transitions of this clock. This clock must be AC- coupled. Differential DCLK Reset. A positive pulse on this input is used to reset the DCLKI and DCLKQ outputs of two or more ADC12D1x00s to synchronize them with other ADC12D1x00s in the system. DCLKI and DCLKQ are always in phase DCLK_RST+/- V2/W1 I with each other, unless one channel is powered down, and do not require a pulse from DCLK_RST to become synchronized. The pulse applied here must meet timing relationships with respect to the CLK input. Although supported, this feature has been superseded by AutoSync. Reference Clock Input. When the AutoSync feature is active, and the ADC12D1x00 is in Slave Mode, the internal divided clocks are synchronized with RCLK+/- Y4/W5 I respect to this input clock. The delay on this clock may be adjusted when synchronizing multiple ADCs. This feature is available in ECM through Control Register (Addr: Eh). 4 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADC12D1000 ADC12D1600 |
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