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ADS42JB46IRGC25 Arkusz danych(PDF) 10 Page - Texas Instruments |
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ADS42JB46IRGC25 Arkusz danych(HTML) 10 Page - Texas Instruments |
10 / 63 page ADS42JB46 SBAS621B – JULY 2013 – REVISED SEPTEMBER 2015 www.ti.com 7.8 Digital Characteristics The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, and IOVDD = 1.8 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS (RESET, SCLK, SEN, SDATA, PDN_GBL, STBY, CTRL1, CTRL2, MODE)(1) All digital inputs support 1.8-V and 3.3-V VIH High-level input voltage 1.2 V logic levels All digital inputs support 1.8-V and 3.3-V VIL Low-level input voltage 0.4 V logic levels SEN 0 µA IIH High-level input current RESET, SCLK, SDATA, PDN_GBL, STBY, 10 µA CTRL1, CTRL2, MODE SEN 10 µA IIL Low-level input current RESET, SCLK, SDATA, PDN_GBL, STBY, 0 µA CTRL1, CTRL2, MODE DIGITAL INPUTS (SYNC~P, SYNC~M, SYSREFP, SYSREFM) VIH High-level input voltage 1.3 V VIL Low-level input voltage 0.5 V VCM_DIG Input common-mode voltage 0.9 V DIGITAL OUTPUTS (SDOUT, OVRA, OVRB) DRVDD VOH High-level output voltage DRVDD V – 0.1 VOL Low-level output voltage 0.1 V DIGITAL OUTPUTS (JESD204B Interface: DA[0,1], DB[0,1])(2) VOH High-level output voltage IOVDD V VOL Low-level output voltage IOVDD – 0.4 V |VOD| Output differential voltage 0.4 V VOCM Output common-mode voltage IOVDD – 0.2 V Transmitter terminals shorted to any voltage Transmitter short-circuit current –100 100 mA between –0.25 V and 1.45 V Single-ended output impedance 50 Ω Output capacitance inside the device, COUT Output capacitance 2 pF from either output to ground (1) The RESET, SCLK, SDATA, PDN_GBL, STBY, CTRL1, CTRL2, and MODE pins have a 150-k Ω (typical) internal pulldown resistor to ground. The SEN pin has a 150-k Ω (typical) pullup resistor to AVDD. (2) 50- Ω, single-ended, external termination to IOVDD. 7.9 Reset Timing (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Delay from AVDD and DRVDD power-up to active RESET t1 Power-on delay 1 ms pulse 10 ns t2 Reset pulse width Active RESET signal pulse width 1 µs t3 Register write delay Delay from RESET disable to SEN active 100 ns (1) Typical values are at 25°C and minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = 85°C, unless otherwise noted. 10 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: ADS42JB46 |
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