Zakładka z wyszukiwarką danych komponentów |
|
ADS42JB46IRGC25 Arkusz danych(PDF) 11 Page - Texas Instruments |
|
ADS42JB46IRGC25 Arkusz danych(HTML) 11 Page - Texas Instruments |
11 / 63 page PowerSupply AVDD,DRVDD RESET SEN t 1 t 2 t 3 R/W A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Register Address <5:0> Register Data <7:0> SDATA SCLK tSCLK tDSU tDH SEN tSLOADS tSLOADH RESET 0 = 0 ADS42JB46 www.ti.com SBAS621B – JULY 2013 – REVISED SEPTEMBER 2015 7.10 Serial Interface Timing (1) PARAMETER MIN TYP MAX UNIT fSCLK SCLK frequency (equal to 1 / tSCLK) > dc 20 MHz tSLOADS SEN to SCLK setup time 25 ns tSLOADH SCLK to SEN hold time 25 ns tDSU SDIO setup time 25 ns tDH SDIO hold time 25 ns (1) Typical values are at 25°C, minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = 85°C, AVDD3V = 3.3 V, and AVDD = DRVDD = IOVDD = 1.8 V, unless otherwise noted. Figure 1. Serial Register Write Timing Diagram NOTE: After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin. Figure 2. Reset Timing Diagram Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: ADS42JB46 |
Podobny numer części - ADS42JB46IRGC25 |
|
Podobny opis - ADS42JB46IRGC25 |
|
|
Link URL |
Polityka prywatności |
ALLDATASHEET.PL |
Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |