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ADS8331IRGET Arkusz danych(PDF) 11 Page - Texas Instruments |
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ADS8331IRGET Arkusz danych(HTML) 11 Page - Texas Instruments |
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11 / 57 page  CONVST EOC (activelow) CS SCLK SDO SDI MSB 1 - MSB 2 - MSB 3 - MSB '1' '0' '1' '1' High-Z High-Z LSB TAG2 TAG1 LSB+1 '0' '0' TAG0 X X X X X X X t H1 t D3 t SCLK t SU4 t H3 t D1 t D2 t SU5 t D4 t SU2 t WL1 ADS8331, ADS8332 www.ti.com SBAS363D – DECEMBER 2009 – REVISED OCTOBER 2015 7.8 Timing Characteristics: VA = 5 V At TA = –40°C to 85°C, and VA = VBD = 5 V, unless otherwise noted. (1) (2) MIN TYP MAX UNIT External, fCCLK = 1/2 fSCLK 0.5 10.5 MHz fCCLK Frequency, conversion clock, CCLK Internal 10.9 11.5 12.6 MHz tSU1 Setup time, rising edge of CS to EOC(3) Read while converting 1 CCLK tH1 CS hold time with respect to EOC(3) Read while sampling 20 ns tWL1 Pulse duration, CONVST low 40 ns tWH1 Pulse duration, CS high 40 ns tSU2 Setup time, rising edge of CS to EOS Read while sampling 20 ns tH2 CS hold time with respect to EOS Read while converting 20 ns tSU3 Setup time, falling edge of CS to first falling edge of SCLK 8 ns tWL2 Pulse duration, SCLK low 12 tSCLK – tWH2 ns tWH2 Pulse duration, SCLK high 11 tSCLK – tWL2 ns I/O clock only 25 ns I/O and conversion clocks 47.6 1000 ns tSCLK Cycle time, SCLK I/O clock, daisy-chain mode 25 ns I/O and conversion clocks, 47.6 1000 ns daisy-chain mode tD1 Delay time, falling edge of SCLK to SDO invalid 10-pF load 5 ns tD2 Delay time, falling edge of SCLK to SDO valid 10-pF load 20 ns tD3 Delay time, falling edge of CS to SDO valid, SDO MSB output 10-pF load 20 ns tSU4 Setup time, SDI to falling edge of SCLK 8 ns tH3 Hold time, SDI to falling edge of SCLK 8 ns tD4 Delay time, rising edge of CS to SDO 3-state 10-pF load 10 ns tSU5 Setup time, last falling edge of SCLK before rising edge of CS 10 ns tH4 Hold time, last falling edge of SCLK before rising edge of CS 2 ns tSU6 (4) Setup time, rising edge of SCLK to rising edge of CS 10 ns tH5 (4) Hold time, rising edge of SCLK to rising edge of CS 2 ns tD5 Delay time, falling edge of CS to deactivation of INT 10-pF load 20 ns (1) All input signals are specified with tr = tf = 1.5 ns (10% to 90% of VBD) and timed from a voltage level of (VIL + VIH)/2. (2) See the timing diagrams. (3) The EOC and EOS signals are the inverse of each other. (4) Applies to the 5th or 17th rising SCLK when sending 4-bit or 16-bit commands, respectively, to the ADS8331/32. Figure 1. Read While Sampling (Shown With Manual-Trigger Mode) Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: ADS8331 ADS8332 |
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