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DAC3482IRKDT Arkusz danych(PDF) 11 Page - Texas Instruments |
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DAC3482IRKDT Arkusz danych(HTML) 11 Page - Texas Instruments |
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11 / 106 page  DAC3482 www.ti.com SLAS748F – MARCH 2011 – REVISED AUGUST 2015 ZAY Package Pin Functions (continued) PIN I/O DESCRIPTION NAME NO. IOUTIP F14 O I-Channel DAC current output. Connect directly to ground if unused. IOUTIN E14 O I-Channel DAC complementary current output. Connect directly to ground if unused. IOUTQP J14 O Q-Channel DAC current output. Connect directly to ground if unused. IOUTQN K14 O Q-Channel DAC complementary current output. Connect directly to ground if unused. D5, D6, G5, H5, IOVDD I Supply voltage for all digital I/O. (3.3 V) L5, L6 PLL loop filter connection. If not using the clock multiplying PLL, the LPF pin can be left LPF D12 I unconnected. LVPECL output strobe positive input. This positive/negative pair is captured with the rising edge of OSTRP A9 I DACCLKP/N. It is used for multiple DAC synchronization. If unused it can be left unconnected. OSTRN B9 I LVPECL output strobe negative input. (See the OSTRP description above.) Optional LVDS positive input parity bit. The PARITYP/N LVDS pair has an internal 100- Ω PARITYP N5 I termination resistor. If unused it can be left unconnected. PARITYN P5 I Optional LVDS negative input parity bit. PLLAVDD C11, D11 I PLL analog supply voltage. (3.3 V) SCLK P9 I Serial interface clock. Internal pull-down. SDENB P10 I Active low serial data enable, always an input to the DAC3482. Internal pull-up. SDIO P11 I/O Serial interface data. Bi-directional in 3-pin mode (default) and 4-pin mode. Internal pull-down. Uni-directional serial interface data in 4-pin mode. The SDO pin is three-stated in 3-pin interface SDO P12 O mode (default). Active high asynchronous hardware power-down input. Internal pull-down. If SLEEP pin is set to SLEEP B8 I logic HIGH before and during device power-up and initialization, the fuse_sleep bit in register 0x1B, bit 11 must be written after register 0x23 during device initialization register setup. Optional LVDS SYNC positive input. The SYNCP/N LVDS pair has an internal 100- Ω termination SYNCP A5 I resistor. If unused it can be left unconnected. SYNCN B5 I LVDS SYNC negative input. Active low input for chip RESET, which resets all the programming registers to their default state. RESETB N10 I Internal pull-up. Transmit enable active high input. Internal pull-down. To enable analog output data transmission, set sif_txenable in register config3 to 1b or pull CMOS TXENABLE N9 I TXENABLE pin to high. To disable analog output, set sif_txenable to 0b and pull CMOS TXENABLE pin to low. The DAC output is forced to midscale. This pin is used for factory testing. Internal pull-down. Leave unconnected for normal TESTMODE A8 O operation. Digital supply voltage. This supply pin is also used for factory fuse programming. Connect to VFUSE D7 I DACVDD for normal operation. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: DAC3482 |
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