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DAC3482IZAYR Arkusz danych(PDF) 7 Page - Texas Instruments |
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DAC3482IZAYR Arkusz danych(HTML) 7 Page - Texas Instruments |
7 / 106 page DAC3482 www.ti.com SLAS748F – MARCH 2011 – REVISED AUGUST 2015 RKD Package Pin Functions (continued) PIN I/O DESCRIPTION NAME NO. LVDS positive input data bits 0 through 15. Internal 100- Ω termination resistor. Data format relative to A7, A8, B9, DATACLKP/N clock is Double Data Rate (DDR) and can be transferred in either byte-wide or word- B10, A12, wide mode. In byte-wide mode the unused pins can be left unconnected. A13, A14, A15, B17, D15P is most significant data bit (MSB) in word-wide mode D[15..0]P I B18, B19, D7P is most significant data bit (MSB) in byte-wide mode B20, A23, D0P is least significant data bit (LSB) A24, B23, B24 The order of the bus can be reversed via config2 revbus bit. B7, B8, A10, A11, B11, B12, B13, B14, A19, D[15..0]N I LVDS negative input data bits 0 through 15. (See D[15:0]P description above.) A20, A21, A22, B21, B22, A26, A27 DACCLKP A3 I Positive external LVPECL clock input for DAC core with a self-bias. DACCLKN B3 I Complementary external LVPECL clock input for DAC core. (see the DACCLKP description above.) A35, A39, DAC core supply voltage. (1.2 V). It is recommended to isolate this supply from CLKVDD and DACVDD I A43 DIGVDD. LVDS positive input data clock. Internal 100- Ω termination resistor. Input data D[15:0]P/N is latched DATACLKP A16 I on both edges of DATACLKP/N (Double Data Rate). DATACLKN B15 I LVDS negative input data clock. (See DATACLKP description above.) A6, A9, A25, DIGVDD I Digital supply voltage. (1.2 V). It is recommended to isolate this supply from CLKVDD and DACVDD. A28 Used as external reference input when internal reference is disabled through config27 extref_ena = EXTIO A34 I/O 1b. Used as internal reference output when config27 extref_ena = 0b (default). Requires a 0.1- μF decoupling capacitor to AGND when used as reference output. LVDS frame indicator positive input. Internal 100- Ω termination resistor. The main functions of this input are to reset the FIFO or to be used as a syncing source. These two functions are captured with FRAMEP B16 I the rising edge of DATACLKP/N. The signal captured by the falling edge of DATACLKP/N can be used as a block parity bit. The FRAMEP/N signal should be edge-aligned with D[15:0]P/N. FRAMEN A18 I LVDS frame indicator negative input. (See the FRAMEP description above.) C1, C2, C3, C4, B32, GND B33, B38, I These pins are ground for all supplies. B39, Thermal Pad IOUTIP B36 O I-Channel DAC current output. Connect directly to ground if unused. IOUTIN B37 O I-Channel DAC complementary current output. Connect directly to ground if unused. IOUTQP B35 O Q-Channel DAC current output. Connect directly to ground if unused. IOUTQN B34 O Q-Channel DAC complementary current output. Connect directly to ground if unused. IOVDD B6, A17, B25 I Supply voltage for all digital I/O. (3.3 V) LPF A1 I/O PLL loop filter connection. If not using the clock multiplying PLL, the LPF pin can be left unconnected. LVPECL output strobe positive input. This positive/negative pair is captured with the rising edge of OSTRP A2 I DACCLKP/N. It is used to sync the divided-down clocks and FIFO output pointer in Dual Sync Sources Mode. If unused it can be left unconnected. OSTRN B2 I LVPECL output strobe negative input. (See the OSTRP description) Optional LVDS positive input parity bit. The PARITYP/N LVDS pair has an internal 100- Ω termination PARITYP B26 I resistor. If unused it can be left unconnected. PARITYN A29 I Optional LVDS negative input parity bit. PLLAVDD B1 I PLL analog supply voltage. (3.3 V) SCLK A31 I Serial interface clock. Internal pull-down. SDENB B28 I Active low serial data enable, always an input to the DAC3482. Internal pull-up. Serial interface data. Bi-directional in 3-pin mode (default) and uni-directional in 4-pin mode. Internal SDIO A30 I/O pull-down. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: DAC3482 |
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