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54F174DM Arkusz danych(PDF) 2 Page - National Semiconductor (TI) |
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54F174DM Arkusz danych(HTML) 2 Page - National Semiconductor (TI) |
2 / 8 page Unit LoadingFan Out 54F74F Pin Names Description UL Input IIH IIL HIGHLOW Output IOH IOL D0–D5 Data Inputs 1010 20 mA b06 mA CP Clock Pulse Input (Active Rising Edge) 1010 20 mA b06 mA MR Master Reset Input (Active LOW) 1010 20 mA b06 mA Q0–Q5 Outputs 50333 b 1 mA20 mA Functional Description The ’F174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs The Clock (CP) and Mas- ter Reset (MR) are common to all flip-flops Each D input’s state is transferred to the corresponding flip-flop’s output following the LOW-to-HIGH Clock (CP) transition A LOW input to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs The ’F174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage ele- ments Truth Table Inputs Outputs MR CP Dn Qn LX X L H L HH H L LL H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial L e LOW-to-HIGH Clock Transition Logic Diagram TLF9489 – 4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 2 |
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