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SN74AUP2G07DSFR Arkusz danych(PDF) 11 Page - Texas Instruments |
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SN74AUP2G07DSFR Arkusz danych(HTML) 11 Page - Texas Instruments |
11 / 26 page 1A 1Y 2A 2Y 11 SN74AUP2G07 www.ti.com SCES748D – SEPTEMBER 2009 – REVISED FEBRUARY 2016 Product Folder Links: SN74AUP2G07 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated 8 Detailed Description 8.1 Overview The SN74AUP2G07 device is a dual buffer gate with open-drain outputs that operate from 0.8 V to 3.6 V. The output of this dual buffer/driver is open-drain, and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.The Ioff feature also allows for live insertion. 8.2 Functional Block Diagram 8.3 Feature Description • Wide operating VCC range of 0.8 V to 3.6 V • 3.6-V I/O tolerant to support down translation • Input hysteresis allows slow input transition and better switching noise immunity at the input • Ioff feature allows voltages on the inputs and outputs when VCC is 0 V • Low noise due to slower edge rates 8.4 Device Functional Modes Table 1 is the function table for SN74AUP2G07. Table 1. Function Table INPUT A OUTPUT Y H H/Z L L |
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