2

SRG8

8

10

7

15

2

EN3

C2

R

C1

1D

G

RCK

CLR

SRCK

SER IN

3

5

4

11

6

13

12

9

14

DRAIN0

DRAIN1

DRAIN2

DRAIN3

DRAIN4

DRAIN5

DRAIN6

DRAIN7

SER OUT

2

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TPIC6C595

SLIS061D – JULY 1998 – REVISED SEPTEMBER 2015

TPIC6C595 Power Logic 8-Bit Shift Register

Outputs are low-side, open-drain DMOS transistors

1 Features

with output ratings of 33-V to 100-mA continuous

1

•

sink-current capability. Each output provides a

•

Avalanche Energy, 30 mJ

current limit decreases as the junction temperature

•

Eight Power DMOS Transistor Outputs of 100-mA

increases for additional device protection. The device

Continuous Current

also provides up to 2500 V of ESD protection when

•

250-mA Current Limit Capability

tested using the human-body model and the 200-V

•

ESD Protection, 2500 V

machine model.

•

Output Clamp Voltage, 33 V

The TPIC6C595 is characterized for operation over

•

Devices are Cascadable

the operating case temperature range of

−40°C to

125°C.

•

Low-Power Consumption

Device Information(1)

2 Applications

PART NUMBER

PACKAGE

BODY SIZE (NOM)

•

Instrumentation Clusters

SOIC (16)

9.90 mm × 3.91 mm

•

Tell-Tale Lamps

TPIC6C595

TSSOP (16)

5.00 mm × 4.40 mm

•

LED Illumination and Controls

PDIP (16)

19.30 mm × 6.35 mm

•

Automotive Relay or Solenoids

(1) For all available packages, see the orderable addendum at

•

Drivers

the end of the data sheet.

Logic Symbol

3 Description

The TPIC6C595 is a monolithic, medium-voltage,

low-current power 8-bit shift register designed for use

in systems that require relatively moderate load

power such as LEDs. The device contains a built-in

voltage clamp on the outputs for inductive transient

protection. Power driver applications include relays,

solenoids, and other low-current or medium-voltage

loads.

This device contains an 8-bit serial-in, parallel-out

shift register that feeds an 8-bit D-type storage

register. Data transfers through both the shift and

storage registers on the rising edge of the shift

register clock (SRCK) and the register clock (RCK),

respectively. The device transfers data out the serial

output (SER OUT) port on the rising edge of SRCK.

The storage register transfers data to the output

buffer when shift register clear (CLR) is high. When

CLR is low, the input shift register is cleared. When

output enable (G) is held high, all data in the output

This symbol is in accordance with

buffers is held low and all drain outputs are off. When

ANSI/IEEE Std 91-1984 and IEC

G is held low, data from the storage register is

Publication 617-12.

transparent to the output buffers. When data in the

output buffers is low, the DMOS transistor outputs are

off. When data is high, the DMOS transistor outputs

have sink-current capability. The SER OUT allows for

cascading of the data from the shift register to

additional devices.

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.