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TS33002-M000QFNR Arkusz danych(PDF) 10 Page - Semtech Corporation |
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TS33002-M000QFNR Arkusz danych(HTML) 10 Page - Semtech Corporation |
10 / 16 page TS33001/2/3 Final Datasheet Rev 1.6 January 15, 2016 www.semtech.com 10 of 16 Semtech Proprietary & Confidential External Component Selection The internal compensation is optimized for a 10uF output capacitor and a 1uH inductor. To keep the output ripple low, a low ESR (less than 20mOhm) ceramic is recommended. For optimal over-current protection, inductor should be able to handle the 3.7A for the 3A version, 2.7A for the 2A version and 1.7A for the 1A version without saturation. Application Using A Multi-Layer PCB To maximize the efficiency of this package for application on a single layer or multi-layer PCB, certain guidelines must be followed when laying out this part on the PCB. The following are guidelines for mounting the exposed pad IC on a Multi-Layer PCB with ground a plane. Solder Pad (Land Pattern) Package Thermal Pad Thermal Via's Package Outline Package and PCB Land Configuration For a Multi-Layer PCB JEDEC standard FR4 PCB Cross-section: (square) Package Solder Pad Component Traces 4 Plane 2 Plane 1.5748mm Thermal Via 1.5038 - 1.5748 mm Component Trace (2oz Cu) 1.0142 - 1.0502 mm Ground Plane (1oz Cu) Thermal Isolation Power plane only Package Solder Pad (bottom trace) 0.5246 - 0.5606 mm Power Plane (1oz Cu) 0.0 - 0.071 mm Board Base & Bottom Pad Multi-Layer Board (Cross-sectional View) In a multi-layer board application, the thermal vias are the primary method of heat transfer from the package thermal pad to the internal ground plane. The efficiency of this method depends on several factors, including die area, number of thermal vias, thickness of copper, etc. |
Podobny numer części - TS33002-M000QFNR |
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Podobny opis - TS33002-M000QFNR |
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