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SPCA751A-P101 Arkusz danych(PDF) 3 Page - List of Unclassifed Manufacturers

Numer części SPCA751A-P101
Szczegółowy opis  a single chip signal processor optimized for MPEG audio decoding and voice recording
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Producent  ETC [List of Unclassifed Manufacturers]
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Preliminary
SPCA751A-P101
3
Function Description
The SPCA751A is a single-chip CMOS microprocessor optimized for real-time MPEG audio decoding and
speech/audio recording.
SPCA751A decodes the encoded MPEG audio data according to the commands passed through the Serial
Control/Data I/O Interface by the host processor, the host processor can also check the status of decoding process by
the use of this interface. Refer to Programming Guide for command definitions
In the digital recorder mode, speech/Audio is sampled at 8Khz by the on-chip ADC into 10-bit digital words, after
encoding, the datum is compressed into a data rate of 4.8Kbps or 32Kbps.
Decoded audio PCM data are output to external DAC through a programmable normal/I
2S PCM interface, this
interface is compliant to most of the common audio DACs.
The embedded PLL is capable of providing the 27 MHz system clock derived from a 16.934MHz clock source
! Serial Control/Data I/O Interface
The host controller uses this interface to transfer MPEG bit-stream with the SPCA751A and to command the
SPCA751A during the recording/decoding process. This interface consists of seven pins:
Pin
# 12
FCEB2
Frame Decoded Indicator generated by the SPCA751A
Pin
# 13
FCEB1
Data Request Flag generated by the SPCA751A
Pin
# 44
SCLK1
Bit Clock controlled by the host processor
Pin
#
1
DT1
Data from the SPCA751A to the host processor
Pin
#
2
TFS1
Transmit Frame Synchronization controlled by the host processor
Pin
#
3
DR1
Data from the host processor to the SPCA751A
Pin
#
4
RFS1
Receive Frame Synchronization controlled by the host processor
"
FCEB1 - Data Request Flag
The FCEB1 flag generated by the SPCA751A informs the status of the decoding/encoding process. When FCEB1
is high, it indicates that the SPCA751A is ready to receive data/command or to transfer data, the host processor is
allowed to start the communication; When FCEB1 is low, the SPCA751A is busy processing internally and no I/O tasks
could be taken, the commands sent by the host processor during low FCEB1 are not accepted by the SPCA751A and
may cause the SPCA751A run into an unknown state.
SPCA
751A
FCEB1
FCEB2
SCLK
RFS1
TFS1
DR1
DT1
Host
Controller


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