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SPCA751A-P101 Datasheet(Arkusz danych) 4 Page - List of Unclassifed Manufacturers

Numer części SPCA751A-P101
Szczegółowy opis  a single chip signal processor optimized for MPEG audio decoding and voice recording
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Producent  ETC [List of Unclassifed Manufacturers]
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Preliminary
SPCA751A-P101
4
"
FCEB2 - Frame Decoded Indicator
Each time the SPCA751A has decoded one frame (512 bytes) of data, it changes the state of FCEB2 (either high
to low or low to high) and progresses to the next frame. By counting the number of state-changes, the host processor
is able to know the time elapsed in decoding.
"
Host Command
The host commands consist of 8-bit command and 8-bit ID, totally 16-bit long. (Refer to the SPCA751A
Programming Guide for command definitions) At the falling edges of SCLK1, the SPCA751A checks whether the RFS1
is high. Once it is high, the 16-bit long command is sampled at the following 16 consecutive falling edges of SCLK1
with MSB first. After the LSB is sent, the host processor should send at least one more cycle of SCLK1 to the
SPCA751A.
"
Host processor writes 512 bytes to the SPCA751A
At the falling edges of SCLK1, the SPCA751A checks whether the RFS1 is high. Once it is high, the 512-byte long
data is sampled at the following 512x8 consecutive falling edges of SCLK1. RFS1 should remain high before the MSB
of the last word. After the LSB of the last word is sent, the host processor should send at least three more cycles of
SCLK1 to the SPCA751A.
Timing Requirements
PARAMETER
MIN.
MAX.
UNIT
TFS
RFS1 setup before SCLK1 falls low
2
ns
TFH
RFS1 hold after SCLK1 falls low
2
ns
TDS
DR1 setup before SCLK1 falls low
3
ns
TDH
DR1 hold after SCLK1 falls low
3
ns
TSCLK
SCLK1 period
16
*
ns
* The maximum period of SCLK1 depends on the sampling rate of the decoded data, too long a SCLK1
period makes the real-time decoding impossible.
SCLK1
RFS1
DR1
b15
b14
b1
b0
T
FS
T
FH
T
DS
T
DH
T
SCLK
SCLK1
RFS1
DR1
b15
b14
b0
b15
T
FS
T
DS
T
DH
T
SCLK
b0
Last word
255 words
T
FH




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