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SPCA751A-P101 Arkusz danych(PDF) 5 Page - List of Unclassifed Manufacturers |
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SPCA751A-P101 Arkusz danych(HTML) 5 Page - List of Unclassifed Manufacturers |
5 / 13 page Preliminary SPCA751A-P101 5 " Host processor reads 512 bytes from the SPCA751A To read data from the SPCA751A, the host processor first asserts the TFS1 at the falling edges of SCLK1, then the 512-byte long data is sampled out from the SPCA751A at the following 512x8 consecutive rising edges of SCLK1. The host processor is supposed to latch-in the data at the falling edges of SCLK1. TFS1 should remain high before the MSB of the last word. After the LSB of the last word is received, the host processor should send at least three more cycles of SCLK1 to the SPCA751A. Timing Requirements PARAMETER MIN. MAX. UNIT TFS TFS1 setup before SCLK1 falls low 2 ns TFH TFS1 hold after SCLK1 falls low 2 ns TSCLK SCLK1 period 16 ns Switching Characteristics PARAMETER MIN. MAX. UNIT TD DT1 access 5 ns TDH DT1 hold after SCLK1 falls low TSCLK / 2 ns ! PLL An independent analog power is applied through pin 41 VSSP and pin 42 VDDP to supply the power for the internal PLL. An oscillation circuit is built externally on pin 39 OSCIN and pin 40 OSCOUT. 16.934MHz Crystal pin 40 OSCOUT pin 39 OSCIN Oscillation Circuit 12 pF 12 pF 10 M Ohm SCLK1 RFS1 DR1 b15 b0 b15 T FS T SCLK b0 Last word 255 words T FH b14 T D T DH |
Podobny numer części - SPCA751A-P101 |
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Podobny opis - SPCA751A-P101 |
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