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AD6643-200EBZ Arkusz danych(PDF) 6 Page - Analog Devices |
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AD6643-200EBZ Arkusz danych(HTML) 6 Page - Analog Devices |
6 / 40 page AD6643 Data Sheet Rev. C | Page 6 of 40 AD6643-200 AD6643-250 Parameter1 Temperature Min Typ Max Min Typ Max Unit SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 30 MHz 25°C 92 90 dBc fIN = 90 MHz 25°C 91 88 dBc Full 80 dBc fIN = 140 MHz 25°C 88 86 dBc fIN = 185 MHz 25°C 88 85 dBc Full 79 dBc fIN = 220 MHz 25°C 84 85 dBc WORST OTHER HARMONIC OR SPUR fIN = 30 MHz 25°C −94 −94 dBc fIN = 90 MHz 25°C −94 −93 dBc Full −80 dBc fIN = 140 MHz 25°C −95 −92 dBc fIN = 185 MHz 25°C −94 −92 dBc Full −80 dBc fIN = 220 MHz 25°C −93 −88 dBc TWO TONE SFDR fIN = 184.12 MHz, 187.12 MHz (−7 dBFS) 25°C 88 88 dBc CROSSTALK2 Full 95 95 dB FULL POWER BANDWIDTH3 25°C 1000 1000 MHz 1 For a complete set of definitions, see the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation. 2 Crosstalk is measured at 100 MHz with −1 dBFS on one channel and with no input on the alternate channel. 3 Full power bandwidth is the bandwidth for the ADC inputs at which the spectral power of the fundamental frequency is reduced by 3 dB. DIGITAL SPECIFICATIONS—AD6643-200/AD6643-250 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, DCS enabled, default SPI, unless otherwise noted. Table 3. Parameter Temperature Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.3 3.6 V p-p Input Voltage Range Full AGND AVDD V Input Common-Mode Range Full 0.9 1.4 V Input Current Level High Full 10 22 µA Low Full −22 −10 µA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ SYNC INPUT Logic Compliance CMOS/LVDS Internal Bias Full 0.9 V Input Voltage Range Full AGND AVDD V Input Voltage Level High Full 1.2 AVDD V Low Full AGND 0.6 V |
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