Data Sheet

AD6643

Rev. C | Page 9 of 40

Timing Diagrams

VIN

CLK+

CLK–

DCO–

DCO+

D0

(LSB)

PARALLEL INTERLEAVED

CHANNEL MULTIPLEXED

(ODD/EVEN) MODE

CHANNEL MULTIPLEXED

(ODD/EVEN) MODE

D11

(MSB)

0/D0±

(LSB)

CH A

N – 10

CH B

N – 10

CH A

N – 9

CH B

N – 9

CH A

N – 8

CH B

N – 8

CH A

N – 7

CH B

N – 7

CH A

N – 6

CH A

N – 10

CH B

N – 10

CH A

N – 9

CH B

N – 9

CH A

N – 8

CH B

N – 8

CH A

N – 7

CH B

N – 7

CH A

N – 6

0

N – 10

CH A0

N – 10

0

N – 9

CH A0

N – 9

0

N – 8

CH A0

N – 8

0

N – 7

CH A0

N – 7

0

N – 6

CH A9

N – 10

CH A10

N – 10

CH A9

N – 9

CH A10

N – 9

CH A9

N – 8

CH A10

N – 8

CH A9

N – 7

CH A10

N – 7

CH A9

N – 6

0

N – 10

CH B0

N – 10

0

N – 9

CH B0

N – 9

0

N – 8

CH B0

N – 8

0

N – 7

CH B0

N – 7

0

N – 6

CH B9

N – 10

CH B10

N – 10

CH B9

N – 9

CH B10

N – 9

CH B9

N – 8

CH B10

N – 8

CH B9

N – 7

CH B10

N – 7

CH B9

N – 6

CHANNEL A

D9/D10±

(MSB)

0/D0±

(LSB)

CHANNEL B

D9/D10±

(MSB)

N – 1

N

N + 1

N + 2

N + 3

N + 4

N + 5

.

.

.

.

.

.

.

.

.

CHANNEL A AND

CHANNEL B

Figure 2. LVDS Modes for Data Output Timing Latency. NSR Disabled (Enabling NSR Adds an Additional Three Clock Cycles of Latency)

SYNC

CLK+

Figure 3. SYNC Timing Inputs