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AD6679BBPZRL7-500 Arkusz danych(PDF) 5 Page - Analog Devices

Numer części AD6679BBPZRL7-500
Szczegółowy opis  135 MHz BW IF Diversity Receiver
Download  81 Pages
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD6679BBPZRL7-500 Arkusz danych(HTML) 5 Page - Analog Devices

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Data Sheet
AD6679
Rev. B | Page 5 of 81
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling
rate, 1.0 V internal reference (VREF), AIN = −1.0 dBFS, clock divider = 2, default SPI settings, unless otherwise noted.
Table 1.
Parameter
Temperature
Min
Typ
Max
Unit
RESOLUTION
14
Bits
ACCURACY
No Missing Codes
Full
Guaranteed
Offset Error
Full
−0.3
0
+0.3
% FSR
Offset Matching
Full
0
0.3
% FSR
Gain Error
Full
−6.5
0
+6.5
% FSR
Gain Matching
Full
0
5.0
% FSR
Differential Nonlinearity (DNL)
Full
−0.6
±0.5
+0.7
LSB
Integral Nonlinearity (INL)
Full
−4.5
±2.5
+5.0
LSB
TEMPERATURE DRIFT
Offset Error
Full
±3
ppm/°C
Gain Error
Full
−39
ppm/°C
INTERNAL VOLTAGE REFERENCE
Voltage
Full
1.0
V
INPUT REFERRED NOISE
VREF = 1.0 V
25°C
2.04
LSB rms
ANALOG INPUTS
Differential Input Voltage Range (Internal VREF = 1.0 V)
Full
1.46
2.06
2.06
V p-p
Common-Mode Voltage (VCM)
Full
2.05
V
Differential Input Capacitance1
Full
1.5
pF
Analog Full Power Bandwidth
Full
2
GHz
POWER SUPPLY
AVDD1
Full
1.22
1.25
1.28
V
AVDD2
Full
2.44
2.50
2.56
V
AVDD3
Full
3.2
3.3
3.4
V
DVDD
Full
1.22
1.25
1.28
V
DRVDD
Full
1.22
1.25
1.28
V
SPIVDD
Full
1.22
1.8
3.4
V
IAVDD1
Full
464
503
mA
IAVDD2
Full
396
455
mA
IAVDD32
Full
89
100
mA
IDVDD (Default SPI—NSR Mode)
Full
141
164
mA
IDVDD (VDR Mode)
Full
117
138
mA
IDRVDD3
Full
110
123
mA
ISPIVDD
Full
5
6
mA
POWER CONSUMPTION
Total Power Dissipation
Default SPI—NSR Mode3
Full
2.2
2.37
W
VDR Mode3
Full
2.16
2.34
W
Power-Down Dissipation
Full
0.71
W
Standby4
Full
1.4
W
1 Differential capacitance is measured between the VIN+x and VIN−x pins (x = A, B).
2 AVDD3 current changes based on the Buffer Control 1 setting (see Figure 46).
3 Parallel interleaved LVDS mode. The power dissipation on DRVDD changes with the output data mode used.
4 Standby can be controlled by the SPI.


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