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AD9642-170EBZ Arkusz danych(PDF) 9 Page - Analog Devices |
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AD9642-170EBZ Arkusz danych(HTML) 9 Page - Analog Devices |
9 / 28 page Data Sheet AD9642 Rev. B | Page 9 of 28 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 24 CSB 23 SCLK 22 SDIO 21 DCO+ 20 DCO– 19 D12+/D13+ (MSB) 18 D12–/D13– (MSB) 17 DRVDD 1 2 3 4 5 6 7 8 CLK+ CLK– AVDD D0–/D1– (LSB) D0+/D1+ (LSB) D2–/D3– D2+/D3+ DRVDD AD9642 INTERLEAVED LVDS TOP VIEW (Not to Scale) NOTES 1. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. 2. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. Figure 3. LFCSP Pin Configuration (Top View) Table 8. Pin Function Descriptions Pin No. Mnemonic Type Description ADC Power Supplies 8, 17 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 3, 27, 28, 31, 32 AVDD Supply Analog Power Supply (1.8 V Nominal). 0 AGND, Exposed Paddle Ground Analog Ground. The exposed thermal paddle on the bottom of the package provides the analog ground for the part. This exposed paddle must be connected to ground for proper operation. 25 DNC Do Not Connect. Do not connect to this pin. ADC Analog 30 VIN+ Input Differential Analog Input Pin (+). 29 VIN− Input Differential Analog Input Pin (−). 26 VCM Output Common-Mode Level Bias Output for Analog Inputs. This pin should be decoupled to ground using a 0.1 μF capacitor. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. Digital Outputs 5 D0+/D1+ (LSB) Output DDR LVDS Output Data 0/1—True. 4 D0−/D1− (LSB) Output DDR LVDS Output Data 0/1—Complement. 7 D2+/D3+ Output DDR LVDS Output Data 2/3—True. 6 D2−/D3− Output DDR LVDS Output Data 2/3—Complement. 10 D4+/D5+ Output DDR LVDS Output Data 4/5—True. 9 D4−/D5− Output DDR LVDS Output Data 4/5—Complement. 12 D6+/D7+ Output DDR LVDS Output Data 6/7—True. 11 D6−/D7− Output DDR LVDS Output Data 6/7—Complement. 14 D8+/D9+ Output DDR LVDS Output Data 8/9—True. 13 D8−/D9− Output DDR LVDS Output Data 8/9—Complement. 16 D10+/D11+ Output DDR LVDS Output Data 10/11—True. 15 D10−/D11− Output DDR LVDS Output Data 10/11—Complement. 19 D12+/D13+ (MSB) Output DDR LVDS Output Data 12/13—True. 18 D12−/D13− (MSB) Output DDR LVDS Output Data 12/13—Complement. 21 DCO+ Output LVDS Data Clock Output—True. 20 DCO− Output LVDS Data Clock Output—Complement. SPI Control 23 SCLK Input SPI Serial Clock. 22 SDIO Input/output SPI Serial Data I/O. 24 CSB Input SPI Chip Select (Active Low). |
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