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LM25037MT Arkusz danych(PDF) 3 Page - Texas Instruments |
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LM25037MT Arkusz danych(HTML) 3 Page - Texas Instruments |
3 / 37 page UVLO COMP FB RT2 AGND RT1 CS RAMP VCC OUTA OUTB PGND SS RES REF VIN LM25037 14 13 12 11 10 8 9 15 16 1 2 3 4 5 7 6 LM25037, LM25037-Q1 www.ti.com SNVS572E – JULY 2008 – REVISED JANUARY 2016 5 Pin Configuration and Functions PW Package 16-Pin TSSOP Top View Pin Functions PIN I/O DESCRIPTION APPLICATION INFORMATION NO. NAME Modulation ramp for the PWM comparator. This ramp can be a representative of the primary current (current mode) or proportional 1 RAMP I Pulse width modulator ramp to input voltage (feed-forward voltage mode). This pin is reset to ground at the conclusion of every cycle by an internal FET. An external voltage divider from the power source sets the shutdown and standby comparator threshold levels. When UVLO exceeds the 2 UVLO I Line undervoltage lockout 0.45V shutdown threshold, the VCC and REF regulators are enabled. When UVLO exceeds the 1.25V standby threshold, the SS pin is released and the device enters the active mode. 3 COMP I/O Input to the pulse width modulator Output of the error amplifier and input to the PWM comparator. Connected to inverting input of the error amplifier. An internal 1.25-V reference is connected to the noninverting input of the error 4 FB I Feedback amplifier. In isolated applications using an external error amplifier, this pin should be connected to the AGND pin. The resistance connected between RT2 and AGND sets the forced 5 RT2 I Oscillator dead-time control dead-time between switching periods of the alternating outputs. 6 AGND — Analog ground Connect directly to Power Ground. The resistance connected between RT1 and AGND sets the 7 RT1 I Oscillator maximum on-time control oscillator maximum on-time. The sum of this maximum on-time and the forced dead-time (set by RT2) sets the oscillator period. If CS exceeds 250 mV the output pulse will be terminated, entering 8 CS I Current sense input cycle-by-cycle current limit. An internal switch holds CS low for 65 nS after either output switches high to blank leading edge transients. If cycle-by-cycle current limit is reached during any cycle, a 18-µA current is sourced to the external RES pin capacitor. If the RES capacitor voltage reaches 2 V, the soft-start capacitor will be fully 9 RES I/O Restart timer discharged and then released with a pullup current of 1 uA. After the first output pulse (when SS = 1V), the SS pin charging current will increase to the normal level of 100 µA. An external capacitor and an internal 100uA current source set the 10 SS I Soft-start soft-start ramp. The SS current source is reduced to 1 µA following a restart event (RES pin high). 11 PGND — Power ground Connect directly to Analog Ground Alternating gate drive output of the pulse width modulator. Capable 12 OUTB O Output driver of 1.2-A peak source and sink current. Alternating gate drive output of the pulse width modulator. Capable 13 OUTA O Output driver of 1.2-A peak source and sink current. If an auxiliary winding raises the voltage on this pin above the Output of the high voltage start-up regulation set point, the internal start-up regulator will shutdown thus 14 VCC I/O regulator. The VCC voltage is reducing the IC power dissipation. Locally decouple VCC with a 0.47 regulated to 7.7 V. µF or greater capacitor. Copyright © 2008–2016, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM25037 LM25037-Q1 |
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