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TC90104FG Arkusz danych(PDF) 9 Page - Toshiba Semiconductor

Numer części TC90104FG
Szczegółowy opis  Multi System Video Decoder IC
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Producent  TOSHIBA [Toshiba Semiconductor]
Strona internetowa  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TC90104FG Arkusz danych(HTML) 9 Page - Toshiba Semiconductor

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Summary
TC90104FG
©2015 TOSHIBA CORPORATION
Page 9
Rev.1.00
2015/12/01
Fig.5 Typical input level to Composite sync
5.2.5
Operation mode (I/O select) setting
Signal process path (I/O) is selected by I2C-BUS register (Sub00H [D7] RGB_MCD by common on all Bank).
RGB_MCD
=
0: MCD block select (CVBS, Y/C, YCbCr, RGB(D2,D1))
1: RGB block select (RGB (QVGA, VGA, WVGA))
Output format decides by signal process route. ITU-R BT.601 or ITU-R BT.656 is output at route of MCD block, and
RGB 18bit is output at route of RGB block.
The setting of MCD block depend on Bank0, and setting of RGB depend on Bank1 and Bank2.
Input mode
Setting of Sub address: 00H
Active Bank
Setting contents
Video
00(hex)
Bank 0
CVBS/YCbCr input to ITU-R BT.656/601 output
A-RGB
81(hex)
Bank1
RGB(dot by dot) input to RGB 18bit output
gamma of
A-RGB
82(hex)
Bank2
RGB(dot by dot) input to RGB gamma setting
0.3Vp-p


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