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TC90107FG Arkusz danych(PDF) 9 Page - Toshiba Semiconductor |
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TC90107FG Arkusz danych(HTML) 9 Page - Toshiba Semiconductor |
9 / 15 page Summary TC90107FG Page 9 Rev.1.00 2015/11/24 5.2.2 Timing pulse output CON[2:0] pin(terminal No.7, 8, 9) are output terminal. Output signal can select by register. 1. DE (Data Enable) signal DE indicates horizontal and vertical enable picture area for output video signal. DE signal is the signal that is HIGH status at active video period, and LOW status at blanking period. 2. HD signal HD signal indicates the horizontal sync pulse synchronized with output video signal. Setting : pulse width, pulse polarity, phase delay 3. VD signal VD signal indicates the vertical sync pulse synchronized with output video signal. Setting : pulse width, pulse polarity, phase delay 4. FIELD signal FIELD signal indicates ODD/EVEN switch pulse synchronized with output video signal. Field signal is the signal that is HIGH status at even field, and LOW status at odd field, when default setting. Polarity of FIELD signal inverts by register [FLDO_POLE]. 5. UVFLG signal UVFLG signal indicates Cb/Cr switch pulse for 4:2:2 format signal. Polarity of UVFLG signal inverts by register [UVREV]. 5.3 Regulator circuit The regulator circuit of 2.5 V output (3.3 V input) for ADC circuit is built in IC. To use regulator output voltage, it is necessary to connect the output terminal of regulator circuit to the power supply input terminal of an ADC circuit in IC exterior. In addition, please do not use the built-in regulator circuit other than the purpose of this IC operation. When it is no use the built-in regulator, do not supply 3.3 V at 39 pin. Regulator circuit The Input terminal which regulator output 3.3 V Input terminal 2.5 V Output terminal REGVDD33A (39 pin) REG25OUTA (42 pin) ADVDD1 (43 pin) ADVDD2 (54 pin) |
Podobny numer części - TC90107FG |
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Podobny opis - TC90107FG |
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