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ADC08L060CIMT Arkusz danych(PDF) 6 Page - National Semiconductor (TI) |
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ADC08L060CIMT Arkusz danych(HTML) 6 Page - National Semiconductor (TI) |
6 / 19 page Converter Electrical Characteristics (Continued) The following specifications apply for V A =VDR = +3.0VDC,VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 60 MHz at 50% duty cycle. Boldface limits apply for T A =TMIN to TMAX: all other limits TA = 25˚C (Notes 7, 8) Symbol Parameter Conditions Typical (Note 9) Limits (Note 9) Units (Limits) DYNAMIC PERFORMANCE t AJ Aperture Jitter 2 ps rms Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = AGND = DR GND = 0V, unless otherwise specified. Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than AGND or DR GND, or greater than VA or VDR), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance ( θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX=(TJmax − TA)/ θJA. In the 24-pin TSSOP, θJA is 92˚C/W, so PDMAX = 1,358 mW at 25˚C and 706 mW at the maximum operating ambient temperature of 85˚C. Note that the power consumption of this device under normal operation will typically be about 49 mW (40 mW quiescent power + 4 mW reference ladder power+5mWto drive the output bus capacitance). The values for maximum power dissipation listed above will be reached only when the ADC08L060 is operated in a severe fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 k Ω resistor. Machine model is 220 pF discharged through ZERO Ohms. Note 6: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”. Note 7: The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not damage this device. However, errors in the A/D conversion can occur if the input goes above VDR or below GND by more than 100 mV. For example, if VA is 2.7VDC the full-scale input voltage must be ≤2.8VDC to ensure accurate conversions. 20041707 Note 8: To guarantee accuracy, it is required that VA and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Note 9: Typical figures are at TJ = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 10: IDR is the current consumed by the switching of the output drivers and is primarily determined by the load capacitance on the output pins, the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent), IDR =VDR (CO xfO +C1 xf1 +…+C71 xf7) where VDR is the output driver power supply voltage, Cn is the total capacitance on any given output pin, and fn is the average frequency at which that pin is toggling. www.national.com 6 |
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