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ADC10664 Arkusz danych(PDF) 10 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Numer części ADC10664
Szczegółowy opis  10-Bit 360 ns A/D Converter with Input Multiplexer and Sample/Hold
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Producent  NSC [National Semiconductor (TI)]
Strona internetowa  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC10664 Arkusz danych(HTML) 10 Page - National Semiconductor (TI)

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Applications Information (Continued)
with S /H and RD; the input voltage is sampled when CS and
S /H are low, and data is read when CS and RD are low. INT
is reset high on the rising edge of RD.
TABLE 1. Input Multiplexer Programming
ADC10664
S
1
S
0
Channel
00
V
IN0
01
V
IN1
10
V
IN2
11
V
IN3
TABLE 2. Input Multiplexer Programming
ADC10662
S
0
Channel
0V
IN0
1V
IN1
Mode 2
In Mode 2, also called “RD mode”, the S /H and RD pins are
tied together. A conversion is initiated by pulling both pins
low. The A/D converter samples the input voltage and
causes the coarse comparators to become active. An inter-
nal timer then terminates the coarse conversion and begins
the fine conversion. 470 ns (typical) after S /H and RD are
pulled low, INT goes low, indicating that the conversion is
completed. Approximately 20 ns later the data appearing on
the TRI-STATE output pins will be valid. Note that data will
appear on these pins throughout the conversion, but until
INT goes low the data at the output pins will be the result of
the previous conversion.
2.0 REFERENCE CONSIDERATIONS
The ADC10662 and ADC10664 each have two reference in-
puts. These inputs, V
REF+ and VREF−, are fully differential
and define the zero to full-scale range of the input signal.
The reference inputs can be connected to span the entire
supply voltage range (V
REF− = 0V, VREF+ = VCC) for ratio-
metric applications, or they can be connected to different
voltages (as long as they are between ground and V
CC)
when other input spans are required. Reducing the overall
V
REF span to less than 5V increases the sensitivity of the
converter (e.g., if V
REF = 2V, then 1 LSB = 1.953 mV). Note,
however, that linearity and offset errors become larger when
lower reference voltages are used. See the Typical Perfor-
mance Curves for more information. For this reason, refer-
ence voltages less than 2V are not recommended.
In most applications, V
REF− will simply be connected to
ground, but it is often useful to have an input span that is off-
set from ground. This situation is easily accommodated by
the reference configuration used in the ADC10662 and
ADC10664. V
REF− can be connected to a voltage other than
ground as long as the voltage source connected to this pin is
capable of sinking the converter’s reference current (12.5
mA Max @ V
REF = 5V). If VREF− is connected to a voltage
other than ground, bypass it with multiple capacitors.
Since the resistance between the two reference inputs can
be as low as 400
Ω, the voltage source driving the reference
inputs should have low output impedance. Any noise on ei-
ther reference input is a potential cause of conversion errors,
so each of these pins must be supplied with a clean, low
noise voltage source. Each reference pin should be by-
passed with a 10 µF tantalum and a 0.1 µF ceramic.
3.0 THE ANALOG INPUT
The ADC10662 and ADC10664 sample the analog input
voltage once every conversion cycle. When this happens,
the input is briefly connected to an impedance approximately
equal to 600
Ω in series with 35 pF. Short-duration current
spikes can therefore be observed at the analog input during
normal operation. These spikes are normal and do not de-
grade the converter’s performance.
Large source impedances can slow the charging of the sam-
pling capacitors and degrade conversion accuracy. There-
fore, only signal sources with output impedances less than
500
Ω should be used if rated accuracy is to be achieved at
the minimum sample time (250 ns maximum). If the sam-
pling time is increased, the source impedance can be larger.
If a signal source has a high output impedance, its output
should be buffered with an operational amplifier. The opera-
tional amplifier’s output should be well-behaved when driving
a switched 35 pF/600
Ω load. Any ringing or voltage shifts at
the op amp’s output during the sampling period can result in
conversion errors.
Correct conversion results will be obtained for input voltages
greater than GND − 50 mV and less than V+ + 50 mV. Do not
allow the signal source to drive the analog input pin more
than 300 mV higher than AV
CC and DVCC, or more than 300
mV lower than GND. If an analog input pin is forced beyond
these voltages, the current flowing through the pin should be
limited to 5 mA or less to avoid permanent damage to the IC.
The sum of all the overdrive currents into all pins must be
less than 20 mA. When the input signal is expected to extend
more than 300 mV beyond the power supply limits, some
sourt of protection scheme should be used. A simple network
using diodes and resistors is shown in
Figure 4.
www.national.com
10


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