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ADC12130 Arkusz danych(PDF) 11 Page - National Semiconductor (TI) |
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ADC12130 Arkusz danych(HTML) 11 Page - National Semiconductor (TI) |
11 / 41 page AC Electrical Characteristics (Continued) Note 7: Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above VA+ or 5V below GND will not damage this device. However, errors in the A/D conversion can occur (if these diodes are forward biased by more than 50 mV) if the input voltage magnitude of selected or unselected analog input go above VA+ or below GND by more than 50 mV. As an example, if VA+ is 4.5 VDC, full-scale input voltage must be ≤4.55 VDC to ensure accurate conversions. Note 8: To guarantee accuracy, it is required that the VA+ and VD+ be connected together to the same power supply with separate bypass capacitors at each V + pin. Note 9: With the test condition for VREF (VREF+−VREF−) given as +4.096V, the 12-bit LSB is 1.0 mV. For VREF = 2.5V, the 12-bit LSB is 610 µV. Note 10: Typicals are at TJ =TA = 25˚C and represent most likely parametric norm. Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero (see Figure 2 and Figure 3). Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the average value of the code transitions be- tween −1 to 0 and 0 to +1 (see Figure 4). Note 14: Total unadjusted error includes offset, full-scale, linearity and multiplexer errors. Note 15: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together. Note 16: Channel leakage current is measured after the channel selection. Note 17: Timing specifications are tested at the TTL logic levels, VOL = 0.4V for a falling edge and VOL = 2.4V for a rising edge. TRI-STATE output voltage is forced to 1.4V. Note 18: The ADC12130 family’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will re- sult in a maximum repeatability uncertainty of 0.2 LSB. Note 19: If SCLK and CCLK are driven from the same clock source, then tA is 6, 10, 18 or 34 clock periods minimum and maximum. Note 20: The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device. Therefore, the output data from these modes are not an indication of the accuracy of a conversion result. DS012079-4 DS012079-5 FIGURE 1. Transfer Characteristic www.national.com 11 |
Podobny numer części - ADC12130 |
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Podobny opis - ADC12130 |
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