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ADC12138CIN Arkusz danych(PDF) 10 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Numer części ADC12138CIN
Szczegółowy opis  Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
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Producent  NSC [National Semiconductor (TI)]
Strona internetowa  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC12138CIN Arkusz danych(HTML) 10 Page - National Semiconductor (TI)

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AC Electrical Characteristics (Continued)
The following specifications apply for (V
+ =V
A+=VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V
common-mode voltage) or (V
+ =V
A+=VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V
common-mode voltage), V
REF− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, VREF− and VREF+
≤ 25Ω,f
CK =fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA =TJ =
T
MIN to TMAX; all other limits TA =TJ = 25˚C. (Note 17) (Continued)
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 10)
(Note 11)
(Limits)
t
SET-UP
Set-Up Time of CS Falling Edge to
50
ns (min)
Serial Data Clock Rising Edge
t
DELAY
Delay from SCLK Falling
0
5
ns (min)
Edge to CS Falling Edge
t
1H,t0H
Delay from CS Rising Edge to
R
L = 3k, CL = 100 pF
70
100
ns (max)
DO TRI-STATE®
t
HDI
DI Hold Time from Serial Data
5
15
ns (min)
Clock Rising Edge
t
SDI
DI Set-Up Time from Serial Data
5
10
ns (min)
Clock Rising Edge
t
HDO
DO Hold Time from Serial Data
R
L = 3k, CL = 100 pF
35
65
ns (max)
Clock Falling Edge
5
ns (min)
t
DDO
Delay from Serial Data Clock
50
90
ns (max)
Falling Edge to DO Data Valid
t
RDO
DO Rise Time, TRI-STATE to High
R
L = 3k, CL = 100 pF
10
40
ns (max)
DO Rise Time, Low to High
10
40
ns (max)
t
FDO
DO Fall Time, TRI-STATE to Low
R
L = 3k, CL = 100 pF
15
40
ns (max)
DO Fall Time, High to Low
15
40
ns (max)
t
CD
Delay from CS Falling Edge
45
80
ns (max)
to DOR Falling Edge
t
SD
Delay from Serial Data Clock Falling
45
80
ns (max)
Edge to DOR Rising Edge
C
IN
Capacitance of Logic Inputs
10
pF
C
OUT
Capacitance of Logic Outputs
20
pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed speci-
fications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA+orVD+), the current at that pin should be limited to 30 mA.
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, θJA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD =(TJmax − TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
TJmax = 150˚C. The typical thermal resistance (θJA) of these parts when board mounted follow:
Thermal
Part Number
Resistance
θ
JA
ADC12130CIN
53˚C/W
ADC12130CIWM
70˚C/W
ADC12132CIMSA
134˚C/W
ADC12138CIN
40˚C/W
ADC12138CIWM
50˚C/W
ADC12138CIMSA
125˚C/W
Note 5: The human body model is a 100 pF capacitor discharged through a 1.5 k
Ω resistor into each pin.
Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post 1986 National Semi-
conductor Linear Data Book for other methods of soldering surface mount devices.
www.national.com
10


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