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ADC12451CMJ Arkusz danych(PDF) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Numer części ADC12451CMJ
Szczegółowy opis  Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold
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Producent  NSC [National Semiconductor (TI)]
Strona internetowa  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC12451CMJ Arkusz danych(HTML) 6 Page - National Semiconductor (TI)

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Electrical Characteristics (Continued)
Note 7
A diode exists between AVCC and DVCC as shown below
TLH11025 – 5
To guarantee accuracy it is required that the AVCC and DVCC be connected together to a power supply with separate bypass filters at each VCC pin
Note 8
Accuracy is guaranteed at fCLK e 35 MHz At higher or lower clock frequencies accuracy may degrade see the typical performance characteristic curves
Note 9
Typicals are at TJ e 25 C and represent most likely parametric norm
Note 10
Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level)
Note 11
Positive linearity error is defined as the deviation of the analog value expressed in LSBs from the straight line that passes through positive full scale and
zero For negative linearity error the straight line passes through negative full scale and zero (See
Figures 1b and 1c )
Note 12
The ADC12451’s self-calibration technique ensures linearity full scale and offset errors as specified but noise inherent in the self-calibration process will
result in a repeatability uncertainty of g020 LSB
Note 13
If TA changes then an Auto-Zero or Auto-Cal cycle will have to be re-started see the typical performance characteristic curves
Note 14
After an Auto-Zero or Auto-Cal cycle at the specified power supply extremes
Note 15
When using the WR control to start a conversion if the clock is asynchronous to the rising edge of WR an uncertainty of one clock period will exist in the
end of the interval of tA therefore making tA end a minimum 6 clock periods or a maximum 7 clock periods after the rising edge of WR If the falling edge of the
clock is synchronous to the rising edge of WR then tA will end exactly 65 clock periods after the rising edge of WR This does not occur when S H control is used
Note 16
The CAL line must be high before a conversion is started
Note 17
The specifications for these parameters are valid after an Auto-Cal cycle has been completed
Note 18
The ADC12451 reference ladder is composed solely of capacitors
Note 19
A military RETS electrical test specification is available on request At time of printing the ADC12451CMJ883 RETS specification complies fully with the
boldface
limits in this column
TLH11025 – 6
FIGURE 1a Transfer Characteristic
6


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