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ADC12D040CIVS Arkusz danych(PDF) 4 Page - National Semiconductor (TI) |
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ADC12D040CIVS Arkusz danych(HTML) 4 Page - National Semiconductor (TI) |
4 / 22 page Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description ANALOG I/O 15 2 V INA+ V INB+ Non-Inverting analog signal Inputs. With a 2.0V reference voltage each input signal level is 2.0 V P-P centered on VCM. 16 1 V INA− V INB− Inverting analog signal Input. With a 2.0V reference voltage the input signal level is from 2.0 V P-P centered on VCM. This pin may be connected to V CM for single-ended operation, but a differential input signal is required for best performance. 7V REF Reference input. This pin should be bypassed to AGND with a 0.1 µF monolithic capacitor. V REF is 2.0V nominal and should be between 1.0V to 2.4V. 11 INT/EXT REF V REF select pin. With a logic low at this pin the internal 2.0V reference is selected. With a logic high on this pin an external reference voltage should be applied to V REF input pin 7. 13 5 V RPA V RPB These pins are high impedance reference bypass pins only. Connect a 0.1 µF capacitor from each of these pins to AGND. DO NOT connect anything else to these pins. 12 6 V RNA V RNB 14 4 V RMA V RMB DIGITAL I/O 60 CLK Digital clock input. The range of frequencies for this input is 100 kHz to 50 MHz (typical) with guaranteed performance at 40 MHz. The input is sampled on the rising edge of this input. 22 41 OEA OEB OEA and OEB are the output enable pins that, when low, enables their respective TRI-STATE data output pins. When either of these pins is high, the corresponding outputs are in a high impedance state. 59 PD PD is the Power Down input pin. When high, this input puts the converter into the power down mode. When this pin is low, the converter is in the active mode. 21 OF Output Format pin. A logic low on this pin causes output data to be in straight binary. A logic high on this pin causes the output data to be in 2’s complement format. www.national.com 4 |
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