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TPA3255D2DDV Arkusz danych(PDF) 6 Page - Texas Instruments |
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TPA3255D2DDV Arkusz danych(HTML) 6 Page - Texas Instruments |
6 / 29 page 6 TPA3255 SLASEA8 – FEBRUARY 2016 www.ti.com Product Folder Links: TPA3255 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT PVDD_x Half-bridge supply DC supply voltage, RL = 4Ω 12 51 53.5 V DC supply voltage, RL ≥ 6Ω 12 53.5 56.5 GVDD_x Supply for logic regulators and gate-drive circuitry DC supply voltage 10.8 12 13.2 V VDD Digital regulator supply voltage DC supply voltage 10.8 12 13.2 V RL(BTL) Load impedance Output filter inductance within recommended value range 2.7 4 Ω RL(SE) 1.5 3 RL(PBTL) 1.6 2 LOUT(BTL) Output filter inductance Minimum output inductance at IOC 5 μH LOUT(SE) 5 LOUT(PBTL) 5 FPWM PWM frame rate selectable for AM interference avoidance; 1% Resistor tolerance Nominal 575 600 625 kHz AM1 475 500 525 AM2 430 450 470 R(FREQ_ADJ) PWM frame rate programming resistor Nominal; Master mode 9.9 10 10.1 k Ω AM1; Master mode 19.8 20 20.2 AM2; Master mode 29.7 30 30.3 CPVDD PVDD close decoupling capacitors 1.0 μF ROC Over-current programming resistor Resistor tolerance = 5%, RL = 4Ω 22 30 k Ω Resistor tolerance = 5%, RL ≥ 6Ω 30 ROC(LATCHED) Over-current programming resistor Resistor tolerance = 5%, RL = 4Ω 47 64 k Ω Resistor tolerance = 5%, RL ≥ 6Ω 64 V(FREQ_ADJ) Voltage on FREQ_ADJ pin for slave mode operation Slave mode 3.3 V TJ Junction temperature 0 125 °C (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) Thermal data are obtained with 85°C heat sink temperature using thermal compound with 0.7W/mK thermal conductivity and 2mil thickness. In this model heat sink temperature is considered to be the ambient temperature and only path for dissipation is to the heatsink. 7.4 Thermal Information THERMAL METRIC(1) TPA3255 UNIT DDV 44-PINS HTSSOP JEDEC STANDARD 4 LAYER PCB FIXED 85°C HEATSINK TEMPERATURE(2) RθJA Junction-to-ambient thermal resistance 50.7 2.5(2) °C/W RθJC(top) Junction-to-case (top) thermal resistance 0.36 0.2 RθJB Junction-to-board thermal resistance 24.4 n/a ψJT Junction-to-top characterization parameter 0.19 0.5 ψJB Junction-to-board characterization parameter 24.2 n/a RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a |
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