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AD9635 Arkusz danych(PDF) 11 Page - Analog Devices

Numer części AD9635
Szczegółowy opis  Dual, 12-Bit, 80 MSPS/125 MSPS, Serial LVDS 1.8 V Analog-to-Digital Converter
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
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AD9635 Arkusz danych(HTML) 11 Page - Analog Devices

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Data Sheet
AD9635
Rev. B | Page 11 of 36
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 8. Pin Configuration, Top View
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
0
AGND,
Exposed Pad
The exposed paddle is the only ground connection on the chip. It must be soldered to the analog
ground of the PCB to ensure proper functionality and heat dissipation, noise, and mechanical strength
benefits.
1, 24, 25, 28 29, 32
AVDD
1.8 V Supply Pins for ADC Analog Core Domain.
2, 3
CLK+, CLK−
Differential Encode Clock for LVPECL, LVDS, or 1.8 V CMOS Inputs.
4
SDIO/PDWN
Data Input/Output in SPI Mode (SDIO). Bidirectional SPI data I/O with 30 kΩ internal pull-down.
Power-Down in Non-SPI Mode (PDWN). Static control of chip power-down with 30 kΩ internal pull-down.
5
SCLK/DFS
SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down.
Data Format Select in Non-SPI Mode (DFS). Static control of data output format, with 30 kΩ internal
pull-down. DFS high = twos complement output; DFS low = offset binary output.
6, 19
DRVDD
1.8 V Supply Pins for Output Driver Domain.
7, 8
D1B−, D1B+
Channel B Digital Outputs.
9, 10
D0B−, D0B+
Channel B Digital Outputs.
11, 12
DCO−, DCO+
Data Clock Outputs.
13, 14
FCO−, FCO+
Frame Clock Outputs.
15, 16
D1A−, D1A+
Channel A Digital Outputs.
17, 18
D0A−, D0A+
Channel A Digital Outputs.
20
CSB
SPI Chip Select. Active low enable with 15 kΩ internal pull-up.
21
VREF
1.0 V Voltage Reference Output.
22
VCM
Analog Output Voltage at Mid AVDD Supply. Sets the common-mode voltage of the analog inputs.
23
RBIAS
Sets the analog current bias. Connect this pin to a 10 kΩ (1% tolerance) resistor to ground.
26, 27
VINA−, VINA+
Channel A ADC Analog Inputs.
30, 31
VINB+, VINB−
Channel B ADC Analog Inputs.
24 AVDD
23 RBIAS
22 VCM
21 VREF
20 CSB
19 DRVDD
18 D0A+
17 D0A–
1
2
3
4
5
6
7
8
AVDD
CLK+
CLK–
SDIO/PDWN
SCLK/DFS
DRVDD
D1B–
D1B+
AD9635
TOP VIEW
(Not to Scale)
NOTES
1. THE EXPOSED PADDLE IS THE ONLY GROUND CONNECTION
ON THE CHIP. IT MUST BE SOLDERED TO THE ANALOG GROUND
OF THE PCB TO ENSURE PROPER FUNCTIONALITY AND HEAT
DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS.


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