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AD9613BCPZ-250 Arkusz danych(PDF) 1 Page - Analog Devices |
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AD9613BCPZ-250 Arkusz danych(HTML) 1 Page - Analog Devices |
1 / 36 page 12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) Data Sheet AD9613 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2011–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES SNR = 69.6 dBFS at 185 MHz fIN and 250 MSPS SFDR = 86 dBc at 185 MHz fIN and 250 MSPS −149.9 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and 250 MSPS Total power consumption: 770 mW at 250 MSPS 1.8 V supply voltages LVDS (ANSI-644 levels) outputs Integer 1-to-8 input clock divider (625 MHz maximum input) Sample rates of up to 250 MSPS IF sampling frequencies of up to 400 MHz Internal ADC voltage reference Flexible analog input range 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk Serial port control Energy-saving power-down modes APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Ultrasound equipment Broadband data applications GENERAL DESCRIPTION The AD9613 is a dual 12-bit, analog-to-digital converter (ADC) with sampling speeds of up to 250 MSPS. The AD9613 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user- selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The ADC output data is routed directly to the two external 12-bit LVDS output ports and formatted as either interleaved or channel multiplexed. Flexible power-down options allow significant power savings, when desired. FUNCTIONAL BLOCK DIAGRAM 12 12 REFERENCE SERIAL PORT SCLK SDIO CSB CLK+ CLK– SYNC 1 TO 8 CLOCK DIVIDER AD9613 VIN+A D0± D11± DCO± OR± PDWN OEB VIN–A VIN+B VCM VIN–B NOTES 1. THE D0± TO D11± PINS REPRESENT BOTH THE CHANNEL A AND CHANNE L B LVDS OUTPUT DATA. AVDD AGND DRVDD . . . . . PARALLEL DDR LVDS AND DRIVERS PIPELINE 12-BIT ADC PIPELINE 12-BIT ADC Figure 1. Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. The AD9613 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent. PRODUCT HIGHLIGHTS 1. Integrated dual, 12-bit, 170 MSPS/210 MSPS/250 MSPS ADCs. 2. Fast overrange and threshold detect. 3. Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz. 4. SYNC input allows synchronization of multiple devices. 5. 3-pin, 1.8 V SPI port for register programming and register readback. 6. Pin compatibility with the AD9643, allowing a simple migration up to 14 bits, and with the AD6649 and the AD6643. |
Podobny numer części - AD9613BCPZ-250 |
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Podobny opis - AD9613BCPZ-250 |
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