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AD9690BCPZ-500 Arkusz danych(PDF) 3 Page - Analog Devices

Numer części AD9690BCPZ-500
Szczegółowy opis  14-Bit, 1 GSPS/500 MSPS JESD204B, Analog-to-Digital Converter
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
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AD9690BCPZ-500 Arkusz danych(HTML) 3 Page - Analog Devices

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Data Sheet
AD9690
GENERAL DESCRIPTION
The AD9690 is a 14-bit, 1 GSPS/500 MSPS analog-to-digital
converter (ADC). The device has an on-chip buffer and sample-
and-hold circuit designed for low power, small size, and ease of
use. This device is designed for sampling wide bandwidth
analog signals of up to 2 GHz. The AD9690 is optimized for
wide input bandwidth, high sampling rate, excellent linearity,
and low power in a small package.
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations.
The analog input and clock signals are differential inputs. The
ADC data output is internally connected to two digital down-
converters (DDCs). Each DDC consists of four cascaded signal
processing stages: a 12-bit frequency translator (NCO), and four
half-band decimation filters.
In addition to the DDC blocks, the AD9690 has several
functions that simplify the automatic gain control (AGC)
function in the communications receiver. The programmable
threshold detector allows monitoring of the incoming signal
power using the fast detect output bits of the ADC. If the input
signal level exceeds the programmable threshold, the fast detect
indicator goes high. Because this threshold indicator has low
latency, the user can quickly turn down the system gain to avoid
an overrange condition at the ADC input.
Users can configure the Subclass 1 JESD204B-based high speed
serialized output in a variety of one-, two-, or four-lane con-
figurations, depending on the DDC configuration and the
acceptable lane rate of the receiving logic device. Multiple device
synchronization is supported through the SYSREF± and
SYNCINB± input pins.
The AD9690 has flexible power-down options that allow
significant power savings when desired. All of these features can
be programmed using a 1.8 V to 3.3 V capable 3-wire SPI.
The AD9690 is available in a Pb-free, 64-lead LFCSP and is
specified over the −40°C to +85°C industrial temperature range.
This product is protected by a U.S. patent.
Rev. 0 | Page 3 of 77


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