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ADuM226N0BRIZ-RL Arkusz danych(PDF) 4 Page - Analog Devices

Numer części ADuM226N0BRIZ-RL
Szczegółowy opis  5.0 kV RMS Dual Channel Digital Isolators
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ADuM226N0BRIZ-RL Arkusz danych(HTML) 4 Page - Analog Devices

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ADuM220N/ADuM221N/ADuM225N/ADuM226N
Data Sheet
Rev. 0 | Page 4 of 23
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
AC SPECIFICATIONS
Output Rise/Fall Time
tR/tF
2.5
ns
10% to 90%
Common-Mode Transient
Immunity6
|CMH|
75
100
kV/µs
VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
|CML|
75
100
kV/µs
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
1
IOx is the Channel x output current, where x is A or B.
2
VIxH is the input side logic high.
3
VIxL is the input side logic low.
4
VI is the voltage input.
5
N0 refers to the ADuM220N0/ADuM221N0/ADuM225N0/ADuM226N0 models, and N1 refers to the ADuM220N1/ADuM221N1/ADuM225N1/ADuM226N1 models. See
the Ordering Guide section.
6
|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-
mode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
Table 2. Total Supply Current vs. Data Throughput
1 Mbps
25 Mbps
100 Mbps
Parameter
Symbol
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
SUPPLY CURRENT
ADuM220N/ADuM225N
Supply Current Side 1
IDD1
3.7
6.8
4.2
7.2
6.2
9.3
mA
Supply Current Side 2
IDD2
1.4
2.0
2.2
3.2
4.8
8.1
mA
ADuM221N/ADuM226N
Supply Current Side 1
IDD1
2.6
4.5
3.2
5.4
5.4
8.2
mA
Supply Current Side 2
IDD2
3.0
4.9
3.7
5.9
5.9
8.6
mA
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended
operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width
PW
6.6
ns
Within PWD limit
Data Rate
150
Mbps
Within PWD limit
Propagation Delay
tPHL, tPLH
4.8
6.8
14
ns
50% input to 50% output
Pulse Width Distortion
PWD
0.7
3
ns
|tPLH − tPHL|
Change vs. Temperature
1.5
ps/°C
Propagation Delay Skew
tPSK
7.0
ns
Between any two units at the same
temperature, voltage, and load
Channel Matching
Codirectional
tPSKCD
0.7
3.0
ns
Opposing Direction
tPSKOD
0.7
3.0
ns
Jitter
290
ps p-p
See the Jitter Measurement section
45
ps rms
See the Jitter Measurement section
DC SPECIFICATIONS
Input Threshold
Logic High
VIH
0.7 × VDDx
V
Logic Low
VIL
0.3 × VDDx
V


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