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ADuM1246ARSZ Arkusz danych(PDF) 11 Page - Analog Devices |
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ADuM1246ARSZ Arkusz danych(HTML) 11 Page - Analog Devices |
11 / 24 page Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 5. ADuM1240/ADuM1245 8-Lead SOIC (R-8) Pin Configuration Figure 6. ADuM1240/ADuM1245 20-Lead SSOP (RS-20) Pin Configuration Table 19. ADuM1240/ADuM1245 8-Lead SOIC (R-8) and 20-Lead SSOP (RS-20) Pin Function Descriptions1 8-Lead SOIC Pin No.2 20-Lead SSOP Pin No. Mnemonic Description 1 1 VDD1 Supply Voltage for Isolator Side 1 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the range of 0.01 µF to 0.1 µF between VDD1 and GND1. N/A 2 GND1 Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both to GND1 is recommended. N/A 3 NIC Not Internally Connected. Leave this pin floating. N/A 4 NIC Not Internally Connected. Leave this pin floating. 2 5 VIA Logic Input A. 3 6 VIB Logic Input B. N/A 7 EN1 Refresh and Watchdog Enable 1. In the 20-lead SSOP package, connecting Pin 7 to GND1 enables the input/output refresh and watchdog functionality for Side 1, supporting standard iCoupler operation. Tying Pin 7 to VDD1 disables the refresh and watchdog functionality for the lowest power operation. See the DC Correctness and Low Power Operation section for a description of this mode. EN1 and EN2 must be set to the same logic state. N/A 8 NIC Not Internally Connected. Leave this pin floating. N/A 9 NIC Not Internally Connected. Leave this pin floating. 4 10 GND1 Ground 1. Ground reference for Isolator Side 1. In the 20-lead SSOP package, Pin 2 and Pin 10 are internally connected, and connecting both to GND1 is recommended. 5 11 GND2 Ground 2. Ground reference for Isolator Side 2. In the 20-lead SSOP package, Pin 11 and Pin 19 are internally connected, and connecting both to GND2 is recommended. N/A 12 NIC Not Internally Connected. Leave this pin floating. N/A 13 NIC Not Internally Connected. Leave this pin floating. N/A 14 EN2 Refresh and Watchdog Enable 2. In the 20-lead SSOP package, connecting Pin 14 to GND2 enables the input/output refresh and watchdog functionality for Side 2, supporting standard iCoupler operation. Tying Pin 14 to VDD2 disables the refresh and watchdog functionality for lowest power operation. See the DC Correctness and Low Power Operation section for a description of this mode. EN1 and EN2 must be set to the same logic state. 6 15 VOB Logic Output B. 7 16 VOA Logic Output A. N/A 17 NIC Not Internally Connected. Leave this pin floating. N/A 18 NIC Not Internally Connected. Leave this pin floating. N/A 19 GND2 Ground 2. Ground reference for Isolator Side 2. In the 20-lead SSOP package, Pin 11 and Pin 19 are internally connected, and connecting both to GND2 is recommended. 8 20 VDD2 Supply Voltage for Isolator Side 2 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the range of 0.01 µF to 0.1 µF between VDD2 and GND2. 1 Reference AN-1109 for specific layout guidelines. 2 N/A = not applicable. VDD1 1 VIA 2 VIB 3 GND1 4 VDD2 8 7 6 GND2 5 VOA VOB ADuM1240/ ADuM1245 TOP VIEW (Not to Scale) VDD1 1 GND1 2 NIC 3 NIC 4 VDD2 NIC = NOT INTERNALLY CONNECTED. 20 GND2 19 NIC 18 NIC 17 VIA 5 VOA 16 VIB 6 VOB 15 EN1 7 EN2 14 NIC 8 NIC 13 NIC 9 NIC 12 GND1 10 GND2 11 ADuM1240/ ADuM1245 TOP VIEW (Not to Scale) Rev. A | Page 11 of 24 |
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