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ADuM231E0BRIZ-RL Arkusz danych(PDF) 7 Page - Analog Devices |
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ADuM231E0BRIZ-RL Arkusz danych(HTML) 7 Page - Analog Devices |
7 / 21 page Data Sheet ADuM230D/ADuM230E/ADuM231D/ADuM231E Rev. A | Page 7 of 21 Parameter Symbol Min Typ Max Unit Test Conditions/Comments AC SPECIFICATIONS Output Rise/Fall Time tR/tF 2.5 ns 10% to 90% Common-Mode Transient Immunity7 |CMH| 75 100 kV/μs VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V |CML| 75 100 kV/μs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V 1 150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible. 2 IOx is the Channel x output current, where x = A, B, or C. 3 VIxH is the input side logic high. 4 VIxL is the input side logic low. 5 VI is the voltage input. 6 E0 refers to the ADuM230E0/ADuM231E0 models, D0 refers to the ADuM230D0/ADuM231D0 models, E1 refers to the ADuM230E1/ADuM231E1 models, and D1 refers to the ADuM230D1/ADuM231D1 models. See the Ordering Guide section. 7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VOx) > 0.8 VDDx. |CML| is the maximum common- mode voltage slew rate that can be sustained while maintaining VOx > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Table 6. Total Supply Current vs. Data Throughput 1 Mbps 25 Mbps 100 Mbps Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit SUPPLY CURRENT ADuM230D/ADuM230E Supply Current Side 1 IDD1 5.3 8.7 5.9 9.3 8.2 12.3 mA Supply Current Side 2 IDD2 1.8 3.6 2.6 4.4 5.2 7.4 mA ADuM231D/ADuM231E Supply Current Side 1 IDD1 4.4 7.1 5.0 7.8 7.5 10.1 mA Supply Current Side 2 IDD2 3.4 5.6 4.1 6.3 6.6 8.7 mA ELECTRICAL CHARACTERISTICS—1.8 V OPERATION All typical specifications are at TA = 25°C, VDD1 = VDD2 = 1.8 V. Minimum/maximum specifications apply over the entire recommended operation range: 1.7 V ≤ VDD1 ≤ 1.9 V, 1.7 V ≤ VDD2 ≤ 1.9 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals. Table 7. Parameter Symbol Min Typ Max Unit Test Conditions/Comments SWITCHING SPECIFICATIONS Pulse Width PW 6.6 ns Within PWD limit Data Rate1 150 Mbps Within PWD limit Propagation Delay tPHL, tPLH 5.8 8.7 15 ns 50% input to 50% output Pulse Width Distortion PWD 0.7 3 ns |tPLH − tPHL| Change vs. Temperature 1.5 ps/°C Propagation Delay Skew tPSK 7.0 ns Between any two devices at the same temperature, voltage, and load Channel Matching Codirectional tPSKCD 0.7 3.0 ns Opposing Direction tPSKOD 0.7 3.0 ns Jitter 600 ps p-p See the Jitter Measurement section 90 ps rms See the Jitter Measurement section DC SPECIFICATIONS Input Threshold Voltage Logic High VIH 0.7 × VDDx V Logic Low VIL 0.3 × VDDx V |
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