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CD4724BCN Arkusz danych(PDF) 1 Page - National Semiconductor (TI) |
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CD4724BCN Arkusz danych(HTML) 1 Page - National Semiconductor (TI) |
1 / 8 page TLF6003 February 1988 CD4723BMCD4723BC Dual 4-Bit Addressable Latch CD4724BMCD4724BC 8-Bit Addressable Latch General Description The CD4723B is a dual 4-bit addressable latch with com- mon control inputs including two address inputs (A0 A1) an active low enable input (E) and an active high clear input (CL) Each latch has a data input (D) and four outputs (Q0 – Q3) The CD4724B is an 8-bit addressable latch with three address inputs (A0 – A2) an active low enable input (E) ac- tive high clear input (CL) a data input (D) and eight outputs (Q0 – Q7) Data is entered into a particular bit in the latch when that is addressed by the address inputs and the enable (E) is low Data entry is inhibited when enable (E) is high When clear (CL) and enable (E) are high all outputs are low When clear (CL) is high and enable (E) is low the channel demultiplexing occurs The bit that is addressed has an ac- tive output which follows the data input while all unad- dressed bits are held low When operating in the address- able latch mode (E e CL e low) changing more than one bit of the address could impose a transient wrong address Therefore this should only be done while in the memory mode (E e high CL e low) Features Y Wide supply voltage range 30V to 15V Y High noise immunity 045 VDD (typ) Y Low power TTL fan out of 2 driving 74L compatibility or 1 driving 74LS Y Serial to parallel capability Y Storage register capability Y Random (addressable) data entry Y Active high demultiplexing capability Y Common active high clear Connection Diagrams CD4723B Dual-In-Line Package TLF6003 – 1 Top View CD4724B Dual-In-Line Package TLF6003 – 2 Top View Order Number CD4723B or CD4724B Truth Table Mode Selection E CL Addressed Unaddressed Mode Latch Latch L L Follows Data Holds Previous Data Addressable Latch H L Hold Previous Data Holds Previous Data Memory L H Follows Data Reset to ‘‘0’’ Demultiplexer H H Reset to ‘0’’ Reset to ‘‘0’’ Clear C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A |
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