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ADS1202I Arkusz danych(PDF) 11 Page - Burr-Brown (TI) |
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ADS1202I Arkusz danych(HTML) 11 Page - Burr-Brown (TI) |
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11 / 21 page  ADS1202 11 SBAS275 www.ti.com ANALOG INPUT STAGE Analog Input The input design topology of the ADS1202 is based on a fully differential switched-capacitor architecture. This input stage provides the mechanism to achieve low system noise, high common-mode rejection (90dB), and excellent power-supply rejection. The input impedance of the analog input is depen- dant on the input capacitor and modulator clock frequency (MCLK), which is also the sampling frequency of the modu- lator. Figure 2 shows the basic input structure of the ADS1202. The relationship between the input impedance of the ADS1202 and the modulator clock frequency is: A f MHz IN MCLK Ω ( ) = • 10 7 12 () (1) The input impedance becomes a consideration in designs where the source impedance of the input signal is HIGH. In this case, it is possible for a portion of the signal to be lost across this external source impedance. The importance of this effect depends on the desired system performance. There are two restrictions on the analog input signal to the ADS1202. Under no conditions should the current into or out of the analog inputs exceed 10mA. The absolute input voltage range must stay in the range GND – 0.4V to VDD + 0.3V. If either of the inputs exceed these limits, the input protection diodes on the front end of the converter will begin to turn on. In addition, the linearity of the device is ensured only when the analog voltage applied to either input resides within the range defined by –320mV and +320mV. Modulator The modulator sampling frequency (CLK) can be operated over a range of a few MHz to 12MHz in mode 3. The frequency of MCLK can be decreased to adjust for the clock requirements of the application. The external MCLK must have double the modulator frequency. The modulator topology is fundamentally a 2nd-order, charge- balancing A/D converter, as the one conceptualized in Figure 3. The analog input voltage and the output of the 1-bit Digital-to- Analog Converter (DAC) are differentiated, providing an analog voltage at X2 and X3. The voltage at X2 and X3 are presented to their individual integrators. The output of these integrators progress in a negative or positive direction. When the value of the signal at X4 equals the comparator reference voltage, the output of the comparator switches from negative to positive, or positive to negative, depending on its original state. When the output value of the comparator switches from HIGH to LOW or vice versa, the 1-bit DAC responds on the next clock pulse by changing its analog output voltage at X6, causing the integrators to progress in the opposite direction. The feedback of the modulator to the front end of the integrators forces the value of the integrator output to track the average of the input. FIGURE 2. Input Impedance of the ADS1202. FIGURE 3. Block Diagram of the 2nd-Order Modulator. R SW 350k Ω (typ) Switching Frequency = CLK High Impedance > 1G Ω C INT 7pF (typ) V CM A IN+ R SW 350k Ω (typ) High Impedance > 1G Ω C INT 7pF (typ) 1.5pF 1.5pF A IN– V REF X 4 X 6 Integrator 2 Comparator f CLK DATA D/A Converter X 3 X 2 X(t) f S Integrator 1 |
Podobny numer części - ADS1202I |
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Podobny opis - ADS1202I |
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