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FM25640 Arkusz danych(PDF) 5 Page - Ramtron International Corporation

Numer części FM25640
Szczegółowy opis  64Kb FRAM Serial Memory
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Producent  RAMTRON [Ramtron International Corporation]
Strona internetowa  http://www.ramtron.com
Logo RAMTRON - Ramtron International Corporation

FM25640 Arkusz danych(HTML) 5 Page - Ramtron International Corporation

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Ramtron
FM25640
Rev. 2.1
Aug 2003
5 of 14
Data Transfer
All data transfers to and from the FM25640 occur in
8-bit groups. They are synchronized to the clock
signal (SCK) and they transfer most significant bit
(MSB) first. Serial inputs are clocked in on the rising
edge of SCK. Outputs are driven on the falling edge
of SCK.
Command Structure
There are six commands called op-codes that can be
issued by the bus master to the FM25640. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, are commands
that have no subsequent operations. They perform a
single function such as to enable a write operation.
Second are commands followed by one byte, either in
or out. They operate on the status register. Last are
commands for memory transactions followed by
address and one or more bytes of data.
Table 1. Op-code Commands
Name
Description
Op-code value
WREN
Set Write Enable Latch
00000110b
WRDI
Write Disable
00000100b
RDSR
Read Status Register
00000101b
WRSR
Write Status Register
00000001b
READ
Read Memory Data
00000011b
WRITE
Write Memory Data
00000010b
WREN - Set Write Enable Latch
The FM25640 will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for
write operations. These include writing the status
register and writing the memory.
Sending the WREN op-code causes the internal
Write Enable Latch to be set. A flag bit in the status
register, called WEL, indicates the state of the latch.
WEL=1
indicates
that
writes
are
permitted.
Attempting to write the WEL bit in the status
register has no effect. Completing any write
operation will automatically clear the write-enable
latch and prevent further writes without another
WREN command. Figure 4 below illustrates the
WREN command bus configuration.
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the status register and verifying that WEL=0. Figure
5 below illustrates the WRDI command bus
configuration.
Figure 5. WREN Bus Configuration
Figure 6. WRDI Bus Configuration


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