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SMP1325-085LF Arkusz danych(PDF) 3 Page - Skyworks Solutions Inc. |
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SMP1325-085LF Arkusz danych(HTML) 3 Page - Skyworks Solutions Inc. |
3 / 7 page DATA SHEET • SMP1325-085LF: SURFACE-MOUNT PIN DIODE Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 201648F • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • March 13, 2015 3 Typical Performance Characteristics (TA = 25 °C, Unless Otherwise Noted) 0.1 1 10 100 Forward Current (mA) 0.1 1 10 100 Figure 2. Series Resistance vs Current @ 100 MHz High-Power Switch Design Applications The SMP1325-085LF PIN diode is designed for shunt applications such as reflective switches or shunt-diode attenuator circuits. Compared to other surface-mount packages, the design of the QFN package produces lower thermal resistance and also reduces the effects of the parasitic inductance of the anode bond wires. A cross-sectional view of the SMP1325-085LF PIN diode is shown in Figure 3. The cathode of the die is soldered directly to the top of the exposed paddle. This paddle is composed of copper, so its thermal resistance is very low. The copper ground paddle minimizes the total thermal resistance between the I layer, which is the location where most heat is generated under normal operation, and the surface to which the package is mounted. Minimal thermal resistance between the I layer and the external environment minimizes junction temperature. The electrically equivalent circuit of the SMP1325-085LF PIN diode is shown in Figure 4. The inductances of pins 1 and 2, as well as the inductances of the bond wires are in series with the input and output transmission lines of the external circuit rather than the portion of the circuit that contains the shunt PIN diode. The effects of these parasitic series inductances are negligible, since they add a very small insertion loss to the shunt PIN but have no effect on the isolation that the diode produces when it is forward biased. A cross section of the suggested printed circuit board design is shown in Figure 5. The via shown in this view is critical, both for electrical performance and for thermal performance. It is recommended that several vias should be placed under the entire footprint of the exposed paddle (pin 2) to minimize both electrical inductance to the system ground and thermal resistance to the system heat sink. |
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