ADC08200 datasheet(7/27 Pages) TI1

Numer części	ADC08200

Szczegółowy opis	8-Bit, 20 Msps to 200 Msps, Low Power A/D Converter

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Producent	TI1 [Texas Instruments]

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ADC08200

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SNAS136M – APRIL 2001 – REVISED MARCH 2013

Converter Electrical Characteristics (continued)

The following specifications apply for VA = VDR = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 5 pF, fCLK = 200 MHz at 50% duty

cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C

(1)(2)(3)

Units

Symbol

Parameter

Conditions

Typical (4)

Limits (4)

(Limits)

POWER SUPPLY CHARACTERISTICS

DC Input

69.75

86

mA (max)

IA

Analog Supply Current

fIN = 10 MHz, VIN = FS − 3 dB

69.75

mA

IDR

Output Driver Supply Current

DC Input, PD = Low

0.25

0.6

mA (max)

DC Input, PD = Low

70

86.6

mA (max)

IA + IDR

Total Operating Current

CLK Low, PD = Hi

0.3

mA

DC Input, Excluding Reference

210

260

mW (max)

PC

Power Consumption

CLK Low, PD = Hi

1

mW

FSE change with 2.7V to 3.3V change in

PSRR1

Power Supply Rejection Ratio

54

dB

VA

SNR reduction with 200 mV at 1MHz on

PSRR2

Power Supply Rejection Ratio

45

dB

supply

AC ELECTRICAL CHARACTERISTICS

fC1

Maximum Conversion Rate

230

200

MHz (min)

fC2

Minimum Conversion Rate

10

MHz

tCL

Minimum Clock Low Time

0.87

1.0

ns (min)

tCH

Minimum Clock High Time

0.65

0.75

ns (min)

CLK to Data Invalid, VA = 3.3V to 3.6V, tA

Output Hold Time, Output Falling (5)

2.4

3.3

ns (max)

=

−40°C to +105°C, CL = 8 pF

tOH

CLK to Data Invalid, VA = 3.3V to 3.6V, tA

Output Hold Time, Output Rising (5)

1.9

2.5

ns (max)

=

−40°C to +105°C, CL = 8 pF

2.4

ns (min)

CLK to Data Transition, VA = 3.3V to

Output Delay, Output Falling (5)

3.9

3.6V, VA = −40°C to +105°C, CL = 8 pF

5.1

ns (max)

tOD

2.4

ns (min)

CLK to Data Transition, VA = 3.3V to

Output Delay, Output Rising (5)

3.3

3.6V, tA = −40°C to +105°C, CL = 8 pF

4.0

ns (max)

Output Falling, VA = 3.3V, CL = 8 pF,

0.73

V/ns

tA = −40°C to +105°C

tSLEW

Output Slew Rate(6)

Output Rising, VA = 3.3V, CL = 8 pF,

0.88

V/ns

tA = −40°C to +105°C

Pipeline Delay (Latency)

6

Clock Cycles

tAD

Sampling (Aperture) Delay

CLK Rise to Acquisition of Data

2.6

ns

tAJ

Aperture Jitter

2

ps rms

(5)

These specifications are ensured by design and not tested.

(6)

Typical output slew rate is based upon the maximum tOD and tOH figures.

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