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ADC10DL065CIVS Arkusz danych(PDF) 3 Page - Texas Instruments |
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ADC10DL065CIVS Arkusz danych(HTML) 3 Page - Texas Instruments |
3 / 34 page Output Buffers MUX Duty Cycle Stabilizer Digital Correction Output Buffers Digital Correction 12 OEA OEB DB0-DB9 10 10 DA0-DA9 or D0-D9 (MUX) 21 2 Stage 1 Stage 10 Stage 9 Stage 8 Stage 3 Stage 2 S/H Timing Control 2 10-Stage Pipeline Converter 2 2 2 3 2 2 2 2 2 2 2 Stage 1 Stage 10 Stage 9 Stage 8 Stage 3 Stage 2 S/H Timing Control 2 10-Stage Pipeline Converter 2 2 2 3 2 2 2 2 2 2 2 Internal Reference Reference Select 2 MULTIPLEX 21 12 VINA+ VINA- VINB- VINB+ VRPA VRMA VRNA VRPB VRMB VRNB CLK VREF ADC10DL065 www.ti.com SNAS314B – JUNE 2006 – REVISED APRIL 2013 Block Diagram Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: ADC10DL065 |
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