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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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ADC10040-Q1 Arkusz danych(PDF) 7 Page - Texas Instruments |
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ADC10040-Q1 Arkusz danych(HTML) 7 Page - Texas Instruments |
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7 / 27 page  ADC10040 www.ti.com SNAS224M – JULY 2003 – REVISED APRIL 2013 DC and Logic Electrical Characteristics Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, External VREF = 1.20V, fCLK = 40 MHz, 50% Duty Cycle, CL = 10 pF/pin. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C (1) (2) (3) Symbol Parameter Conditions Min Typ Max Units CLK, DF, STBY, SENSE Logical “1” Input Voltage 2 V Logical “0” Input Voltage 0.8 V Logical “1” Input Current +10 µA Logical “0” Input Current −10 µA D0–D9 OUTPUT CHARACTERISTICS Logical “1” Output Voltage IOUT = −0.5 mA VDDIO − 0.2 V Logical “0” Output Voltage IOUT = 1.6 mA 0.4 V DYNAMIC CONVERTER CHARACTERISTICS(4) 9.4, 9.6 Bits fIN = 11 MHz 9.3 ENOB Effective Number of Bits 9.4, 9.6 Bits fIN = 19 MHz 9.3 58.7, 59.6 dB fIN = 11 MHz 58.1 SNR Signal-to-Noise Ratio 58.6, 59.5 dB fIN = 19 MHz 58 58.6, dB fIN = 11 MHz 59.5 58 SINAD Signal-to-Noise Ratio + Distortion 58.5, dB fIN = 19 MHz 59.4 57.8 −75.9, fIN = 11 MHz −89 dBc −74.7 2nd HD 2nd Harmonic −74.4, fIN = 19 MHz −86 dBc −73 −69.5, fIN = 11 MHz −78 dBc −67.5 3rd HD 3rd Harmonic −68.8, fIN = 19 MHz −77 dBc −66.7 −69.5, fIN = 11 MHz −78 dB −67.5 Total Harmonic Distortion (First 6 THD Harmonics) −68.8, f.IN = 19 MHz −77 dB −66.7 −75.8, fIN = 11 MHz −80 dBc −74.5 Spurious Free Dynamic Range SFDR (Excluding 2nd and 3rd Harmonic) −75.7, fIN = 19 MHz −80 dBc −74.3 (1) To ensure accuracy, it is required that |VDDA–VDDIO| ≤ 100 mV and separate bypass capacitors are used at each power supply pin. (2) With the test condition for 2 VP-P differential input, the 10-bit LSB is 1.95 mV. (3) Typical figures are at TA = TJ = 25°C and represent most likely parametric norms. Test limits are ensured to TI's AOQL (Average Outgoing Quality Level). (4) Optimum dynamic performance will be obtained by keeping the reference input in the +1.2V. Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: ADC10040 |
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