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ADC12C170 Arkusz danych(PDF) 3 Page - Texas Instruments |
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ADC12C170 Arkusz danych(HTML) 3 Page - Texas Instruments |
3 / 29 page AGND VA AGND VA IDC VREF AGND VA VA VA VRM VRN VRP VA AGND ADC12C170 www.ti.com SNAS374E – DECEMBER 2006 – REVISED APRIL 2013 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description ANALOG I/O 3 VIN− Differential analog input pins. The differential full-scale input signal level is two times the reference voltage with each input pin signal 4 VIN+ centered on a common mode voltage, VCM. 43 VRP 45 VRM These pins should each be bypassed to AGND with a low ESL (equivalent series inductance) 0.1 µF capacitor placed very close to the pin to minimize stray inductance. A 0.1 µF capacitor should be placed between VRP and VRN as close to the pins as possible, and a 10 µF capacitor should be placed in parallel. VRP and VRN should not be loaded. VRM may be loaded to 1mA for 44 VRN use as a temperature stable 1.5V reference. It is recommended to use VRM to provide the common mode voltage, VCM, for the differential analog inputs, VIN+ and VIN−. This pin can be used as either the +1.0V internal reference voltage output (internal reference operation) or as the external reference voltage input (external reference operation). To use the internal reference, VREF should be decoupled to AGND with a 0.1 µF, low equivalent series inductance (ESL) capacitor. In this mode, VREF defaults as the output for the internal 1.0V 46 VREF reference. To use an external reference, overdrive this pin with a low noise external reference voltage. The input impedance looking into this pin is 9k Ω. Therefore, to overdrive this pin, the output impedance of the external reference source should be << 9k Ω. This pin should not be used to source or sink current. The full scale differential input voltage range is 2 * VREF. This is a four-state pin controlling the input clock mode and output data format. CLK_SEL/DF = VA, CLK+ and CLK− are configured as a differential clock input. The output data format is 2's complement. CLK_SEL/DF = (2/3)*VA, CLK+ and CLK− are configured as a differential clock input. The output data format is offset binary. 8 CLK_SEL/DF CLK_SEL/DF = (1/3)*VA, CLK+ is configured as a single-ended clock input and CLK − should be tied to AGND. The output data format is 2's complement. CLK_SEL/DF = AGND, CLK+ is configured as a single-ended clock input and CLK − should be tied to AGND. The output data format is offset binary. This is a three-state input controlling Power Down and Sleep modes. PD = VA, Power Down is enabled. In the Power Down state only the reference voltage circuitry remains active and power dissipation is reduced. 7 PD/Sleep PD = VA/2, Sleep mode is enabled. Sleep mode is similar to Power Down mode - it consumes more power but has a faster recovery time. PD = AGND, Normal operation. Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: ADC12C170 |
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