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ADC101S051Q Arkusz danych(PDF) 6 Page - Texas Instruments

Numer części ADC101S051Q
Szczegółowy opis  Single Channel, 200 to 500 ksps, 10-Bit A/D Converter
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IOL
200 2A
IOH
200 2A
1.6 V
To Output Pin
CL
25 pF
ADC101S051
SNAS303I – JULY 2005 – REVISED JANUARY 2014
www.ti.com
ADC101S051 Timing Specifications
The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 4 MHz to 10 MHz, CL = 25 pF, fSAMPLE = 200
ksps to 500 ksps, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
Parameter
Test Conditions
Typ
Limits
Units
tCS
Minimum CS Pulse Width
10
ns (min)
tSU
CS to SCLK Setup Time
10
ns (min)
tEN
Delay from CS Until SDATA TRI-STATE Disabled(1)
20
ns (max)
VA = +2.7V to +3.6V
40
ns (max)
tACC
Data Access Time after SCLK Falling Edge(2)
VA = +4.75V to +5.25V
20
ns (max)
tCL
SCLK Low Pulse Width
0.4 x tSCLK
ns (min)
tCH
SCLK High Pulse Width
0.4 x tSCLK
ns (min)
VA = +2.7V to +3.6V
7
ns (min)
tH
SCLK to Data Valid Hold Time
VA = +4.75V to +5.25V
5
ns (min)
25
ns (max)
VA = +2.7V to +3.6V
5
ns (min)
tDIS
SCLK Falling Edge to SDATA High Impedance(3)
25
ns (max)
VA = +4.75V to +5.25V
5
ns (min)
tPOWER-
Power-Up Time from Full Power-Down
1
µs
UP
(1)
Measured with the timing test circuit shown in Figure 3 and defined as the time taken by the output signal to cross 1.0V.
(2)
Measured with the timing test circuit shown in Figure 3and defined as the time taken by the output signal to cross 1.0V or 2.0V.
(3)
tDIS is derived from the time taken by the outputs to change by 0.5V with the timing test circuit shown in Figure 3. The measured number
is then adjusted to remove the effects of charging or discharging the output capacitance. This means that tDIS is the true bus relinquish
time, independent of the bus loading.
Timing Diagrams
Figure 3. Timing Test Circuit
6
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