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ADC14DC080 Arkusz danych(PDF) 8 Page - Texas Instruments |
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ADC14DC080 Arkusz danych(HTML) 8 Page - Texas Instruments |
8 / 27 page VA AGND To Internal Circuitry I/O ADC14DC080 SNAS463B – SEPTEMBER 2008 – REVISED APRIL 2013 www.ti.com Timing and AC Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.0V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (1) (2) Units Symb Parameter Conditions Typical (3) Limits (Limits) Maximum Clock Frequency 80 MHz (max) Minimum Clock Frequency 20 MHz (min) tCH Clock High Time 6 ns tCL Clock Low Time 6 ns tCONV Conversion Latency 7 Clock Cycles 4.7 ns (min) tOD Output Delay of CLK to DATA Relative to rising edge of CLK 6.8 8.9 ns (max) tSU Data Output Setup Time Relative to DRDY 5.8 4 ns (min) tH Data Output Hold Time Relative to DRDY 6.6 4.6 ns (min) tAD Aperture Delay 0.6 ns tAJ Aperture Jitter 0.1 ps rms (1) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per Absolute Maximum Ratings, Note 4. However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described in the Operating Ratings section. (2) With a full scale differential input of 2VP-P , the 14-bit LSB is 122.1 µV. (3) Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are not ensured. 8 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC14DC080 |
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