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ADC16V130 Arkusz danych(PDF) 4 Page - Texas Instruments |
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ADC16V130 Arkusz danych(HTML) 4 Page - Texas Instruments |
4 / 31 page AGND VA3.0 AGND VA3.0 VA3.0 VDR AGND DRGND D DB D DB D+ D- ADC16V130 SNAS458E – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com PIN DESCRIPTIONS (continued) Pin No. Symbol Equivalent Circuit Function and Connection DIGITAL I/O D0+/- to D3+/- LVDS Data Output. The 16-bit digital output of the data converter is 15 – 22 D4+/- to D7+/- provided on these ports in a full data rate manner. A 100 Ω 25 – 32 D8+/- to D11+/- termination resistor must be placed between each pair of differential 35 – 42 D12+/- to signals at the far end of the transmission line. 45 – 52 D15+/- Over-Range Indicator. Active High. This output is set High when analog input signal exceeds full scale of 16 bit conversion range (<0,> 65535). This signal is asserted 53, 54 OR+/- coincidently with the over-range data word. A 100 Ω termination resistor must be placed between the differential signals at the far end of the transmission. Output Clock. This pin is used to clock the output data. It has the same frequency as the sampling clock. One word of data is output in each cycle of this signal. A 100 Ω termination resistor must be placed 33, 34 OUTCLK+/- between the differential clock signals at the far end of the transmission line. The rising edge of this signal should be used to capture the output data. See the detail Section on Timing Diagrams . This is a three-state pin. PD = VA3.0, then Power Down is enabled. In the Power Down state, only the reference voltage circuitry remains active and power dissipation is reduced. 14 PD PD =VA3.0 * (2/3), then Sleep mode is enabled. In Sleep mode is similar to Power Down mode - it consumes more power but has a faster recovery time. PD = AGND, then Normal operation mode is turned on. This is a four-state pin controlling two parameters: input clock selection and output data format. CLK_SEL/DF = VA3.0, then CLK+ and CLK− are configured as a differential clock input and the output data format is 2's complement. CLK_SEL/DF = VA3.0 * (2/3), then CLK+ and CLK− are configured as a differential clock input and the output data format is offset binary. 1 CLK_SEL/DF CLK_SEL/DF = VA3.0 * (1/3), then CLK+ is configured as a single- ended clock input and CLK − should be tied to AGND. The output data format is 2's complement. CLK_SEL/DF = AGND, then CLK+ is configured as a single-ended clock input and CLK − should be tied to AGND. The output data format is offset binary. POWER SUPPLIES 3.0V Analog Power Supply. These pins should be connected to a 2, 55, 59 VA3.0 Analog Power quiet source and should be decoupled to AGND with 0.1 μF capacitors located close to the power pins. 1.8V Analog Power Supply. These pins should be connected to a 9, 64 VA1.8 Analog Power quiet source and should be decoupled to AGND with 0.1 μF capacitors located close to the power pins. 1.8V Analog/Digital Power Supply. These pins should be connected to 13 VAD1.8 Analog/Digital Power a quiet source and should be decoupled to AGND with 0.1 μF capacitors located close to the power pins. Analog Ground Return. The exposed pad (Pin 0) on back of the 0, 3, 8, 12, AGND Analog Ground package must be soldered to ground plane to ensure rated 56, 60, 63 performance. Output Driver Power Supply. This pin should be connected to a quiet 24, 44 VDR Power voltage source and be decoupled to DRGND with a 0.1 μF capacitor close to the power pins. 23, 43 DRGND Ground Output Driver Ground Return. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 4 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC16V130 |
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